在此篇論文，我們取得業界的八吋晶元為作實驗的樣本，而因為元件逐漸微縮化的關係，因此一些像操作電壓以及一些原先的電性特徵值的改變比不上元件的縮小率，而且因為元件的氧化層面積及厚度也跟著變小，造成許多特徵值上的改變，因此氧化層的重要性逐漸的被人重視。而此實驗是要找出氧化層薄厚是否帶給元件那些特性表現上的不同處及找出崩潰前後電性上有何變化。
在一開始利用步階電壓及定電壓模式對元件做電性上的監控，並利用以往的崩潰定義，來做電性上的分析，以期找出氧化層薄厚之間對元件會有什麼影響，另外試著歸納是否有更確切的方式來定義元件是否崩潰。
以上的實驗我們以安捷倫科技公司(Agilent)所提供的軟體ICS(Interactive Characterization Software)來控制半導體參數分析儀(HP4155B)以及Keithley所提供的4200-SCS system做一連串的自動量測及參數擷取以達成我們的研究。

In this thesis, the sample is an 8inch wafer for 0.15μm technology n-MOSFET’s and p-MOSFET’s and we researched on oxide reliability. As devices scaling down, the device operational voltage and some characteristic still decreases slowly. The area and the thickness of the device oxide layer also decreased that varied the characteristic representation. So the dielectric oxide layer in MOSFET is to pay much attention to people. My experiment focuses on the difference between thin and thick oxide layer and finds the difference of the characteristic between before breakdown and after breakdown.
First, I use ramp voltage test and constant voltage test to confer the difference of the I-V changes. Then I use the past breakdown definition to analyze the I-V curve. I want to find what influence on device between thin and thick oxide layer. Besides, I try to generalize it has the more accurate way to define the device breakdown.
In these experiments, we used ICS (Interactive Characterization Software) to control HP4155B (Semiconductor Parameter Analyzer) produced by Agilent Technologies and 4200-SCS system produced by Keithley to finish various researches.

Abstract (Chinese) I
Abstract (English) II
Acknowledgements III
Contents IV
Figure Captions V
Table Captions X

Chapter 1 Introduction 1
Chapter 2 Measurement introduction
2.1 HP4155B I-V analysis tool 7
2.2 4200-SCS system 7
Chapter 3 Model introduction
3.1 Percolation 10
3.2 The comparison between constant current stress (CCS)
and constant voltage stress (CVS) 11
Chapter 4 Experiment Details, Result and Analysis 16
Chapter 5 Conclusion and Future Study
5.1 Conclusions 31
5.2 Future Study 32
Reference 33

[1] Maes, H.E.; Degraeve, R.; Nigam, T.; De Blauwe, J.; Groeseneken, G.; “Reliability of ultra-thin dielectrics for giga scale silicon technologies” Optoelectronic and Microelectronic Materials Devices, 1998. Proceedings. 1998 Conference on , 1999 ,Page(s): 7 -14
[2] Kundu, S.; Sengupta, S.; Galivanche, R.; “Test challenges in nanometer technologies” European Test Workshop, 2000. Proceedings. IEEE , 2000 Page(s): 83 -90
[3] Oussalah, S.; Nebel, F.; “On the oxide thickness dependence of the time-dependent-dielectric-breakdown” Electron Devices Meeting, 1999. Proceedings., 1999 IEEE Hong Kong , 1999 Page(s): 42 -45
[4] Momose, H.S.; Ohguro, T.; Nakamura, S.; Toyoshima, Y.; Ishiuchi, H.; Iwai, H.; “Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide” VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on , 2001 Page(s): 77 -78
[5] Ono, A.; Fukasaku, K.; Hirai, T.; Makabe, M.; Koyama, S.; Ikezawa, N.; Ando, K.; Suzuki, T.; Imai, K.; Nakamura, N.; “A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip” VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on , 2001 Page(s): 79 -80
[6] Takayanagi, M.; Takagi, S.; Toyoshima, Y.; “Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regime” VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on , 2001 Page(s): 99 -100
[7] Linder, B.P.; Stathis, J.H.; Wachnik, R.A.; Wu, E.; Cohen, S.A.; Ray, A.; Vayshenker, A.; “Gate oxide breakdown under Current Limited Constant Voltage Stress” VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on , 2000 Page(s): 214 -215
[8] Borse, D.G.; Vaidya, S.J.; Chandorkar, A.N.; “Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics” Electron Devices, IEEE Transactions on , Volume: 49 Issue: 4 , Apr 2002 Page(s): 699 -701
[9] Mullen, E.; Leveugle, C.; Molyneaux, J.; Prendergast, J.; Suehle, J.S.; “A technique to predict gate oxide reliability using fast on-line ramped Q/sub BD/ testing” Reliability Physics Symposium Proceedings, 2002. 40th Annual , 2002 Page(s): 292 -297
[10] Yider Wu; Qi Xiang; Bang, D.; Lucovsky, G.; Ming-Ren Lin; “Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides” IEEE Electron Device Letters , Volume: 20 Issue: 6 , Jun 1999 Page(s): 262 -264
[11] Han, L.K.; Bhat, M.; Wristers, D.; Fulford, J.; Kwong, D.L.; “Polarity dependence of dielectric breakdown in scaled SiO2” Electron Devices Meeting, 1994. Technical Digest., International , 11-14 Dec 1994 Page(s): 617 -620
[12] Satake, H.; Toriumi, A.; “Dielectric breakdown mechanism of thin-SiO2 studied by the post-breakdown resistance statistics” VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on , 1999 Page(s): 61 -62
[13] Eriguchi, K.; Niwa, M.; “Correlation between lifetime, temperature, and electrical stress for gate oxide lifetime testing” IEEE Electron Device Letters , Volume: 18 Issue: 12 , Dec 1997 Page(s): 577 -579
[14] Mullen, E.; Leveugle, C.; Molyneaux, J.; Prendergast, J.; Suehle, J. “Relationship between TDDB testing and wafer level ramped QBD testing using both fixed current and current density stressing” Integrated Reliablilty Workshop Final Report, 2001. 2001 IEEE International , 2001 Page(s): 74 -77
[15] Wu, E.Y.; Sune, J.; Nowak, E.; Lai, W.; McKenna, J.; “Weibull slopes, critical defect density, and the validity of stress induced leakage current (SILC) measurements” Electron Devices Meeting, 2001. IEDM Technical Digest. International , 2001 Page(s): 6.3.1 -6.3.4
[16] Min-Yu Tsai; Horng-Chih Lin; Da-Yuan Lee; Tiao-Yuan Huang; “Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide” IEEE Electron Device Letters , Volume: 22 Issue: 7 , Jul 2001 Page(s): 348 -350
[17] Teramoto, A.; Umeda, H.; Azamawari, K.; Kobayashi, K.; Shiga, K.; Komori, J.; Ohno, Y.; Miyoshi, H.; “Study of oxide breakdown under very low electric field” Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International , 1999 Page(s): 66 -71
[18] Stathis, J.H. “Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits” Device and Materials Reliability, IEEE Transactions on , Volume: 1 Issue: 1 , Mar 2001 Page(s): 43 -59
[19] Hongwei Luo; Yunfei En; Xuedong Kong; Xiaoming Zhang; “The different gate oxide degradation mechanism under constant voltage /current stress and ramp voltage stress” Integrated Reliability Workshop Final Report, 2000 IEEE International , 2000 Page(s): 141 -143
[20] Suehle, J.S.; “Ultrathin gate oxide reliability: physical models, statistics, and characterization” Electron Devices, IEEE Transactions on , Volume: 49 Issue: 6 , Jun 2002 Page(s): 958 -971
[21] Satake, H.; Toriumi, A.; “Dielectric breakdown mechanism of thin-SiO2 studied by the post-breakdown resistance statistics” Electron Devices, IEEE Transactions on , Volume: 47 Issue: 4 , Apr 2000 Page(s): 741 -745
[22] Takayanagi, M.; Takagi, S.; Toyoshima, Y.; “Experimental study of gate voltage scaling for TDDB under direct tunneling regime” Reliability Physics Symposium, 2001. Proceedings. 39th Annual. 2001 IEEE International , 2001 Page(s): 380 -385
[23] Nigam, T.; Degraeve, R.; Groeseneken, G.; Heyns, M.M.; Maes, H.E. “Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?” Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International , 31 Mar-2 Apr 1998 Page(s): 62 -69
[24] Alam, M.A.; “SILC as a measure of trap generation and predictor of TBD in ultrathin oxides” Electron Devices, IEEE Transactions on , Volume: 49 Issue: 2 , Feb 2002 Page(s): 226 -231
[25] Suehle, J.S.; “Metrology development at NIST for characterizing wear-out and reliability of thin gate dielectrics” Electrical Insulation and Dielectric Phenomena, 2001 Annual Report. Conference on , 2001 Page(s): 273 -276