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研究生:楊家凱
研究生(外文):Chia-Kai Yang
論文名稱:用於降低測試時間及測試資料量之掃描測試架構
論文名稱(外文):Advanced Scan Architecture for Test Time and Test Volume Reductions
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:82
中文關鍵詞:測試資料量掃描測試架構測試時間
外文關鍵詞:test volumescan architecturetest time
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數位電路的測試中,最被常使用到的測試技術之一是掃描測試技術。然而這項技術往往會面臨到過長的測試時間及過大的測試資料量這兩項最嚴重的問題。而上述的兩項問題將會造成對昂貴測試機台需求的增加。在本篇論文中,我們提出一個用於降低測試時間及測試資料量之掃描測試架構。本架構的基本觀念是在不增加額外的掃入接腳及掃出接腳的前提下去縮短掃描鍊的長度。從我們對 ISCAS-89 Benchmark 電路的實驗中可看出,此架構可同時達到極高的測試時間降低量及測試資料量降低量,特別是對大型的電路其降低量會更明顯。
我們同時也提出了一個新的無失真空間壓縮法 (space compression) 用以設計我們所提測試架構中的空間壓縮電路。此空間壓縮電路包含了 P1 及 P2 這兩塊疊接在一起的電路。P1 中包含了數個單一輸出之同位樹 (parity tree),而 P2 中則是包含了一些邏輯閘。我們所提出的空間壓縮電路可將一個電路的大量輸出腳位壓縮到一個極小的數字。從我們對 ISCAS-85 Benchmark 電路的實驗可看出,若只使用 P1 的話,所有電路的輸出腳位均可被無失真壓縮到三至五個;而再使用 P2 的話,所有電路的輸出腳位均可再被無失真壓縮到只剩一個。而在對 ISCAS-89 Benchmark 電路的實驗中可看出,若只使用 P1 的話,所有電路的輸出腳位 (即代表該電路的原始輸出腳位及所有正反器之輸入腳) 均可被無失真壓縮到三至七個;而再使用 P2 的話,所有電路的輸出腳位均可再被無失真壓縮到最多兩個。
Scan-based techniques are the most commonly used design for test (DFT) techniques for large digital circuits. However, long test time and large amount of test volume are two serious problems in a scan-based design. The above two problems will result in more demand on the expensive automatic test equipment (ATE) which acts as the test sources and sinks during testing. In this thesis, we propose an advanced scan architecture for test time and test volume reductions. The basic idea of this architecture is to shorten the scan chain length without using extra scan-in or scan-out ports. Experimental results on ISCAS-89 benchmark circuits show that the proposed architecture can simultaneously achieve high test time reduction ratio (TTRR) and high test volume reduction ratio (TVRR), especially for large circuits.
We also propose a novel zero-aliasing space compression method for the advanced scan architecture. Our space compressor contains two cascade circuits, P1 and P2. The circuit P1 consists of a number of single-output parity trees, while P2 is composed of several types of logic gates. The proposed space compressor can compress a large number of outputs from a CUT into an extremely small number. Experimental results show that the outputs of all ISCAS-85 benchmark circuits can be compressed into three to five outputs by P1 and further compressed into exactly one output by P2, both without aliasing. As for ISCAS-89 benchmark circuits, the outputs, i.e., the primary outputs (POs) and flip-flops (FFs) input, can be compressed into three to seven outputs by P1 and at most two outputs by further using P2 with zero aliasing.
Chapter 1 Introduction1
1.1 Motivation1
1.2 Introduction to the Advanced Scan Architecture2
1.3 Organization of Thesis4
Chapter 2 Background and Previous Work6
2.1 Background-Input Reduction Method6
2.2 Previous Work8
2.2.1 Test Time Reduction9
2.2.2 Test Volume Reduction10
2.2.3 Space Compression11
Chapter 3 Overview of Advanced Scan Architecture14
3.1 Version-114
3.2 Version-218
Chapter 4 A Novel Space Compression Method22
4.1 Basic Concepts of the Novel Space Compression Technique23
4.2 Definitions, Theorems, and Proofs25
4.3 Space Compression Algorithms35
Chapter 5 Synthesis Procedures44
5.1 Design of Mapping Block44
5.2 Architecture Synthesis Procedures49
5.2.1 Version-149
5.2.2 Version-251
5.3 Architecture Operations during Test Application52
5.3.1 Version-152
5.3.2 Version-256
Chapter 6 Experimental Results60
6.1 Our Space Compression Method60
6.2 Advanced Scan Architecture Version-167
6.3 Advanced Scan Architecture Version-272
Chapter 7 Conclusions77
References80
[1]T. J. Wood, “The Test and Debug Features of the AMD-K7TM Microprocessor,” in Proc. International Test Conference, 1999, pp. 130-136.
[2]R. S. Fetherston, I. P. Shaik, and S. C. Ma, “Testability Features of AMD-K6TM Microprocessor,” In Proc. International Test Conference, 1997, pp. 406-413.
[3]C. A. Chen and S. K. Gupta, “Efficient BIST TPG Design and Test Set Compaction via Input Reduction,” IEEE. Trans. on Computer-Aided Design, vol. 17, no. 8, pp. 692-705, Aug. 1998.
[4]I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Built-in-Self-test Test Pattern Generators,” in Proc. VLSI Test Symposium, 2000, pp. 369-375.
[5]R. Gupta, S. Narayanan, and M. A. Breuer, “Optimal Configuring of Multiple Scan Chains,” IEEE Trans. on Computers, vol. 42, no. 9, pp. 1121-1131, Sep. 1993.
[6]K. J. Lee, J. J. Chen, and C. H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1793-1802, Dec. 1999.
[7]Ilker Hamzaoglu and Janak H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” in Proc. Fault-Tolerant Computing, 1999, pp. 260-267.
[8]Chauchin Su and Kychin Hwang, “A Serial Scan Test Vector Compression Methodology,” In Proc. International Test Conference, 1993, pp. 981-988.
[9]S. J. Wang and S. N. Chiou, “Generating Efficient Tests for Continuous Scan,” In Proc. Design Automation Conference, Jun. 2001, pp. 162-165.
[10]I. Pomeranz, L. N. Reddy, and S. M. Reddy, “COMPACTEST: A Method to generate Compact Test Sets for Combinational Circuits,” IEEE Trans. on CAD, pp. 1040-1049, Jul. 1993.
[11]B. Koenemann, “LFSR-coded Test Patterns for Scan Designs,” in Proc. European Test Conference, 1991, pp. 237-242.
[12]S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” in Proc. International Test Conference, 1992, pp. 120-129.
[13]S.Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers,” in Proc. IEEE/ACM International Conference Computer-Aided Design, 1993, pp. 572-577.
[14]S. Hellebrand, J. Rajski, S. Tarnick, S.Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Trans. on Computers, vol. 44, no. 2, pp. 223-233, Feb. 1995.
[15]N. Zacharia, J. Rajski, and J. Tyszer, “Decompression of Test Data Using Variable-Length Seed LFSRs,” in Proc. VLSI Test Symposium, 1995, pp. 426-433.
[16]N. Zacharia, J. Rajski, J. Tyszer, and J. A. Waicukauski, “Two-Dimensional Test Data Decompressor for Multiple Scan Designs,” in Proc. International Test Conference, 1996, pp. 186-194.
[17]S. Hellebrand, H. G. Liang, and H. J. Wunderlich, “A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,” in Proc. International Test Conference, 2000, pp. 778-784.
[18]H. G. Liang, S. Hellebrand, and H. J. Wunderlich, “Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST,” in Proc. International Test Conference, 2001, pp. 894-902.
[19]J. P. Hayes, “Transition Count Testing of Combinational Logic Circuits,” IEEE Trans. on Comput., vol. c-25, pp. 613-620, 1976.
[20]B. Konemann, J. Mucha, and G. Zwiehoff, “Built-In Logic Block Observation Techniques,” in Proc. IEEE International Test Conference, 1979, pp. 37-41.
[21]J. Savir, “Syndrome-Testable Design of Combinational Circuits,” IEEE Trans. on Comput., vol. c-29, pp. 442-451, 1980.
[22]A. K. Susskind, “Testing by Verifying Walsh Coefficients,” IEEE Trans. on Comput., vol. c-32, pp. 198-201, 1983.
[23]K. Chakrabarty, and J. P. Hayes, “Zero-Aliasing Space Compaction of Test Response Using Multiple Parity Signatures,” IEEE Trans. on VLSI Systems, vol. 6, pp. 309-313, 1998.
[24]S. R. Das, E. M. Petriu, T. F. Barakat, M. H. Assaf, and A. R. Nayak, “Space Compaction Under Generalized Mergeability,” IEEE Trans. on Instrumentation and Measurement, vol. 47, pp. 1283-1293, 1998.
[25]W. B. Jone, “DSC — A SPACE COMPRESSION METHOD,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 2756 -2759,1990.
[26]A. Dmitriev, M. Gossel, K. Chakrabarty, “Robust Space Compaction of Test Responses,” in Proc. Asian Test Symposium, 2002, pp. 254-259.
[27]Bhargab B. Bhattacharya, A. Dmitriev, M. Gössel, and K. Chakrabarty, “Synthesis of Single-Output Space Compactors for Scan-Based Sequential Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 1171-1179, 2002.
[28]Faraday FS8000A Series 0.35um Standard Cell. Faraday Technology Corporation, 2000.
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