臺灣博碩士論文加值系統

本論文提出一個根據金氧半場效電晶體平方根定律來實現的低電壓平方根領域濾波器，並藉由HSPICE模擬和硬體實現來驗證此設計方法的可靠度與可擴充性。此外，利用設計低電壓電路的技巧，在不影響濾波器效能的前提之下，我們成功的將電路的供應電壓降低到1.5伏特。所提出的濾波器架構具有低供應電壓、超過10 MHz的高極點頻率、寬廣的頻率可調範圍以及不錯的線性度與雜訊效能。
低電壓二階帶通濾波器電路以TSMC 0.25 μm 製程實現，經實驗證明電路之極點頻率可以藉由外加電流調整的特性，可調整範圍在4 MHz到10 MHz之間。在線性度方面：三階諧波失真為-44.76 dB, 而且在輸入信號峰對峰值100 mV時，總諧波失真也小於3%。

A low voltage square root domain filter based on the MOSFET square law is proposed in this thesis. Through the verification of HSPICE simulation and hardware implementation, the extendibility and the reliability of the design procedure are proved. Furthermore, the supply voltage is successfully level down to 1.5 V by the level shifter low voltage technique without degrading the performance of the filters. The proposed filter structure has the merits of low power supply voltage operation, high frequency operation, and the wide range of pole frequency tuneability with comparable linearity and noise performance.
The proposed circuit has been fabricated with 0.25 μm CMOS technology. The experimental results have verified the center frequency f0 of the band-pass filter can be electronically tunable in the range of 4 MHz to 10 MHz. The third order intermodulation (IM3) distortion is -44.67 dB and the total harmonic distortion (THD) is less than 3% for signal amplitude of 100 mV.

Chapter 1 INTRODUCTION1
1.1 Background1
1.2 Motivation3
1.3 Thesis organization5
Chapter 2 DESIGN METHODOLOGY OF SRD FILTERS7
2.1 State-space approach8
2.2 The transfer function to state-space equation transformation9
2.2.1 First order filter transformation9
2.2.2 Second order filter transformation10
2.2.3 High order filter transformation15
2.3 The design steps of the Square-root domain filter15
2.3.1 The first low pass filter17
2.3.2 The second order low pass filter19
2.3.3 The second order band pass filter21
2.3.4 The biquad filter23
2.4 The design procedure of the square-root domain filter26
Chapter 3 LOW VOLTAGE SQUARE-ROOT CIRCUIT28
3.1 The stack MOS square-root circuit28
3.2 The design of the low voltage square-root circuit31
3.2.1 The low voltage technique selection31
3.2.2 The level shifter current mirror selection and modification32
3.3 Construction and simulation of the low voltage square-root circuit38
Chapter 4 IMPLEMENTATION OF VARIOUS SRD FILTERS46
4.1 Filter circuit structures modification48
4.1.1 The first low pass filter48
4.1.2 The second order low pass filter50
4.1.3 The second order band pass filter52
4.1.4 The biquad filter55
4.2 The design and simulation of the first order low pass filter57
4.2.1 Using load capacitor C=1 pF for high frequency range57
4.2.2 Using load capacitor C= 10 pF for low frequency range61
4.3 The design and simulation of the second order low pass filter67
4.3.1 Using load capacitor C=1 pF for high frequency range67
4.3.2 Using load capacitor C=10 pF for low frequency range73
4.4 The design and simulation of the second order band pass filter80
4.4.1 Using load capacitor C=1 pF for high frequency range80
4.4.2 Using load capacitor C=10 pF for low frequency range85
4.5 The design and simulation of the biquad filter92
4.5.1 Low pass filter output using the load capacitor C=1 pF for high frequency range92
4.5.2 Low pass filter output using the load capacitor C=10 pF for low frequency range97
4.5.3 Band pass filter output using the load capacitor C=1 pF for high frequency range104
4.5.4 Band pass filter output using the load capacitor C=10 pF for low frequency range109
4.6 Cases discussion: Higher order filter design and simulation116
4.6.1 Case discussion 1: second order band pass filter117
4.6.2 Case discussion 2: third order low pass filter118
4.6.3 Case discussion 3: eighth order low pass filter120
4.6.4 Case discussion 4 : fifth order low pass filter121
4.7 The Monte-Carlo analysis of the square root domain filter122
4.8 Specification conclusion123
Chapter 5 HARDWARE IMPLEMENTATION AND MEASUREMENT124
5.1 The 1.5 V second order band pass filter124
5.1.1 Hardware implementation126
5.1.2 Simulation129
5.1.3 Measurement131
5.2 The 2.5 V second order band pass filter and biquad filter134
5.2.1 Hardware implementation136
5.2.2 Simulation138
5.2.3 Measurement143
Chapter 6 CONCLUSIONS150
6.1 Conclusions150
6.2 Future works152
PUBLICATION LIST154
REFERENCE155

[1]R. W. Adams, “Filtering in the log-domain”, in 63rd AES Conf., New York, 1979, preprint 1470.
[2]D. R. Frey, “Log-domain filtering: an approach to current-mode filtering”, IEE Proc. G, vol. 140, pp. 406-416, 1993.
[3]D. R. Frey, “Exponential state space filters: A generic current mode design strategy,” IEEE Trans. Circuits Syst. I, vol. 43, pp. 34-42, Jan. 1996.
[4]E. M. Drakakis, A. J. Payne, and C. Toumazou, “Log-domain state-space: a systematic transistor-level approach for log-domain filtering”, IEEE Trans. Circuits Syst. II, vol. 46, pp. 290-305, Mar. 1999.
[5]E. M. Drakakis, A. J. Payne, and C. Toumazou, “Log-domain filtering and Bernoulli cell”, IEEE Trans. Circuits Syst. I, vol. 46, no. 5, pp. 559-571, May 1999.
[6]W. Germanovix, G. O’Neill, C. Toumazou, E. M. Drakakis, R. I. Kitney, and T. S. Lande, “Analogue micropowered log-domain tone controller for auditory prostheses,” Electron. Lett., vol. 34, pp. 1051-1052, May 1998.
[7]M. H. Eskiyerli, A. J. Payne, and C. Toumazou, “State-space synthesis of biquads based on the MOSFET square law”, in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, pp. 321-324, 1996.
[8]C. Psychalinos and S. Blassis, “A systematic design procedure for square-root-domain circuits based on the signal flow graph approach”, IEEE Trans. Circuits Syst I, vol. 49, no. 12, pp. 1702-1712, Dec 2002.
[9]G. J. Yu, B. D. Liu, Y. C. Hsu, and C. Y. Huang, “Design of log domain low-pass filters by MOSFET square law”, in Proc. the Second IEEE Asia Pacific Conf. on ASICs, pp. 9-12, 2000.
[10]G. J. Yu, J. J. Chen, H. Y. Lin, B. D. Liu, and C. Y. Huang, “A low-voltage low-power log-domain band-pass filter,” will be presented at 2003 International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, April, 23-25, 2003.
[11]A. J. Lopez-Martin, A. Carlosena, “A 1.5 V CMOS companding filter,” Electron. Lett., vol. 38, pp. 1346-1347, Oct. 2002.
[12]A. J. Lopez-Martin, A. Carlosena, “A 3.3V tunable current-mode square-root domain biquad” IEEE Symp. Circuit and Syst. ISCAS ,vol.5, p.p.5-8, 2000.
[13]J. V. Kumar, K. R. Rao, “A low-voltage low power square-root domain filter”, Asia-Pacific Conference on Circuits and Systems , vol. 2, p.p. 375-378, 2002.
[14]S. S. Rajput, S. S. Jamuar. “Low voltage analog circuit design techniques” IEEE circuit Syst. Mag. vol.1, issue.1 pp.24-42. 2002.
[15]N. S. Nise, Control Systems Engineering. Reading, MA: Addison-Wesley, 1995.
[16]C. Y. Chen, C. Y. Huang, and B. D. Liu, “A current-mode defuzzifier circuit to realize the centroid strategy,” IEE Proc. Circ. Devices Syst., vol. 144, no. 5, pp. 265-271, Oct. 1997.
[17]V. I. Prodanov, M. M. Green, “CMOS current mirrors with reduced input and output voltage requirements”, Electronics Letters , vol.32, no.2 , pp.104 —105, 18 Jan. 1996.
[18]Yonghua Cong, R. L. Geiger, “Cascode current mirrors with low input, output and supply voltage requirements”, in Proc. the 43rd IEEE Midwest Symposium on Circuits and Systems, vol.1, pp.490 —493, 2000.