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研究生:黃昭欽
研究生(外文):Chao-Ching Huang
論文名稱:適應性單晶片網路系統層設計
論文名稱(外文):System Design of an adaptive Network-on-a-Chip
指導教授:周哲民
指導教授(外文):Jer-Min Jou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:126
中文關鍵詞:單晶片網路適應性
外文關鍵詞:adaptiveNOC
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設計一個複雜的SoC系統將會遇到許多挑戰,如TTM,而單晶片網路系統(aNoC)可以有效解決之。它提供了系統設計中實體部分與架構部分之垂直整合,此整合方式可達成各設計層的可重用能力。一單晶片網路系統主要是由四個部分─通訊元件、計算元件、記憶體系統與應用介面所組合而成。計算元件取決於設計者其應用系統的功能而定,其可為一ASIC、一DSP核心或是一般用途處理器。通訊元件則是用來連接上述計算元件,其包含網路連線、網路介面與網路控制器,並具有隨應用系統需求調整路由機制之能力。應用介面則是使用者用來控制整個適應性網路單晶片平台之介面,其包含計算與通訊兩大介面,分別達成平台上不同之功能需求。
此適應性單晶片網路系統將系統之計算與通訊部分分開,使得一設計團隊可以有效率地並行設計一應用系統,並達成高效能之一高度適應性、可重用性及可伸縮性之系統設計平台。
Designing a complex system-on-a-chip (SoC) poses many challenges. The adaptive Networks-on-a-chip (aNoC) is a new architectural template, which can help meet many of these challenges and enable fast time to market for new products. aNoC provides vertical integration of physical and architectural levels in system design, which helps in reuse at various levels of design. An aNoC template is composed of computing and storage resources connected by a switching infrastructure for data communication, and is extremely efficient for an IC design platform.In this paper, an adaptive Networks-On-a-chip, aNoC, template is proposed, which not only provides fast, scalable data transfer, but it also can be easily extended and reconfigured as the system expands and communication patterns change.
Chapter 1 INTRODUCTION
1.1 SoC problems? ………………….........2
1.2 Related work……………………………….........4
1.3 Components of the aNoC………………….........5
1.4 Paper organization……………………….........6
Chapter 2 Perspectives of the aNoC
2.1 Communication Perspective of the aNoC…......8
2.1.1 OSI Reference Model Applied To aNoC………..8
2.1.1.1 Physical Layer — hardware; raw bit stream……..9
2.1.1.2 Data Link Layer — data frame to bits…..……...9
2.1.1.3 Network Layer — addressing and routing………….10
2.1.1.4 Transport Layer — flow control and error-handling.12
2.1.1.5 Session Layer — syncs and sessions…..………..13
2.1.1.6 Presentation Layer — translation………………..14
2.1.1.7 Application/Software Layer — user interface….14
2.1.2 A Communication-Based NoC Example: The Pleiades Platform..14
2.2 Multiprocessor Perspective of the aNoC…………..16
2.3 Platform Perspective of the aNoC………………....18
2.3.1 The Platform-Based Design Flow……….…….....20
2.3.2 Proposed aNoC platform-based design…….......23
Chapter 3 aNoC Communication Components
3.1 Interconnect Network…………….………….........26
3.1.1 Topology consideration……………………........29
3.1.1.1 Homogeneous or Heterogeneous?………………...29
3.1.1.2 Local or global?……………………………......31
3.1.1.3 Proposed topology of the aNoC………….......33
3.1.1.4 Mapping to a 2-D layout……………….........34
3.1.2 Routing (Switching) Algorithm…………….......34
3.1.3 Criteria of the interconnect network performance…..36
3.1.4 Proposed aNoC Interconnect Network………........37
3.1.4.1 Static Network……………………………........37
3.1.4.2 Dynamic Network………………………...........37
3.2 Routers (communication controllers)………….....38
3.2.1 OSI Behaviour Model…………..………….........38
3.2.2 Router Model………………………………..........39
3.2.2.1 Related Router Model……………………........40
3.2.2.1 Proposed Router Model…………………….......41
3.2.2.1.1 General router model……………………......42
3.2.2.1.2 Specific Router Model………………….......50
3.2.3 Router Parameters………. ……..………….......54
3.2.4 Static Switch………………………………….......55
3.2.4.1 Switch Controller (SC)……………………......56
3.2.4.2 Switch Allocator (SA)…………………….......57
3.2.4.3 Switch Fabric……………………………….......57
3.2.4.4 Proposed Static Switch Processor…………....58
3.2.4.5 Static Network Flow Control — Static Ordering..58
3.2.5 Dynamic Switch…………………………............59
3.2.5.1 Switch Controller……………………….…......60
3.2.5.2 Switch Allocator…………………………........60
3.2.5.3 Proposed Dynamic Switch Processor…….......61
3.2.5.5 Dynamic network flow control……………….....62
3.3 Network Interface……………………...…......62
Chapter 4 aNoC Computation Components and Memory System
4.1 aNoC computation components……………….........65
4.1.1 Basic Model………...………………........65
4.1.2 Reconfigurable Structure of the Tile Processor.67
4.1.3 Proposed Tile Processor Structure……...……...67
4.1.3.1 Registers of the tile processor……..…..……68
4.1.3.1.1 Network registers…………..………...……...68
4.1.3.1.2 Special purpose registers……....…...…….69
4.1.3.2 Energy Efficiency Techniques……….……...….70
4.1.4 Threading Mechanism — Featherweight thread……70
4.1.4.1 Fast thread switching — Block Multithreading…71
4.1.4.2 Scheduling for Featherweight Threads……...…..72
4.2 aNoC Memory System……………...……...........72
4.2.1 DMA mode……………...…….............74
4.2.2 Memory Model and Synchronization……………….74
4.2.3 Latency Tolerance of the aNoC Memory………….74
Chapter 5 aNoC Application Interface
5.1 Computation Application Interface (CPAI)……...78
5.2 Communication Application Interface (CMAI)…....79
5.2.1 Physical Layer of the CMAI……………………….81
5.2.2 Network Layer of the CMAI………………….…..82
5.2.3 Transport (User) Layer of the CMAI………....84
5.2.3.1 Message Injection Instructions…………....84
5.2.3.2 Message Extraction Instructions....……..85
5.2.3.3 User-Level Atomicity and the Execution Model...86
5.2.3.4 Implementation of Message Injection/Extraction Instructions….87
5.2.3.4.1 Implementation of Message Injection Interfaces.88
5.2.3.4.2 Implementation of Message Extraction Instruction.……95
5.2.3.5 The User-Level Atomicity Mechanism…….101
Chapter 6 aNoC Integration and Application Mapping
6.1 aNoC platform integration…………........111
6.2 Application Mapping………….....116
6.2.1 Application Mapping Example…………..118
Chapter 7 aNoC Conclusion.....122
Reference……………………...........123
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