設計一個複雜的SoC系統將會遇到許多挑戰，如TTM，而單晶片網路系統(aNoC)可以有效解決之。它提供了系統設計中實體部分與架構部分之垂直整合，此整合方式可達成各設計層的可重用能力。一單晶片網路系統主要是由四個部分─通訊元件、計算元件、記憶體系統與應用介面所組合而成。計算元件取決於設計者其應用系統的功能而定，其可為一ASIC、一DSP核心或是一般用途處理器。通訊元件則是用來連接上述計算元件，其包含網路連線、網路介面與網路控制器，並具有隨應用系統需求調整路由機制之能力。應用介面則是使用者用來控制整個適應性網路單晶片平台之介面，其包含計算與通訊兩大介面，分別達成平台上不同之功能需求。
此適應性單晶片網路系統將系統之計算與通訊部分分開，使得一設計團隊可以有效率地並行設計一應用系統，並達成高效能之一高度適應性、可重用性及可伸縮性之系統設計平台。

Designing a complex system-on-a-chip (SoC) poses many challenges. The adaptive Networks-on-a-chip (aNoC) is a new architectural template, which can help meet many of these challenges and enable fast time to market for new products. aNoC provides vertical integration of physical and architectural levels in system design, which helps in reuse at various levels of design. An aNoC template is composed of computing and storage resources connected by a switching infrastructure for data communication, and is extremely efficient for an IC design platform.In this paper, an adaptive Networks-On-a-chip, aNoC, template is proposed, which not only provides fast, scalable data transfer, but it also can be easily extended and reconfigured as the system expands and communication patterns change.

Chapter 1 INTRODUCTION
1.1 SoC problems? ………………….........2
1.2 Related work……………………………….........4
1.3 Components of the aNoC………………….........5
1.4 Paper organization……………………….........6
Chapter 2 Perspectives of the aNoC
2.1 Communication Perspective of the aNoC…......8
2.1.1 OSI Reference Model Applied To aNoC………..8
2.1.1.1 Physical Layer — hardware; raw bit stream……..9
2.1.1.2 Data Link Layer — data frame to bits…..……...9
2.1.1.3 Network Layer — addressing and routing………….10
2.1.1.4 Transport Layer — flow control and error-handling.12
2.1.1.5 Session Layer — syncs and sessions…..………..13
2.1.1.6 Presentation Layer — translation………………..14
2.1.1.7 Application/Software Layer — user interface….14
2.1.2 A Communication-Based NoC Example: The Pleiades Platform..14
2.2 Multiprocessor Perspective of the aNoC…………..16
2.3 Platform Perspective of the aNoC………………....18
2.3.1 The Platform-Based Design Flow……….…….....20
2.3.2 Proposed aNoC platform-based design…….......23
Chapter 3 aNoC Communication Components
3.1 Interconnect Network…………….………….........26
3.1.1 Topology consideration……………………........29
3.1.1.1 Homogeneous or Heterogeneous?………………...29
3.1.1.2 Local or global?……………………………......31
3.1.1.3 Proposed topology of the aNoC………….......33
3.1.1.4 Mapping to a 2-D layout……………….........34
3.1.2 Routing (Switching) Algorithm…………….......34
3.1.3 Criteria of the interconnect network performance…..36
3.1.4 Proposed aNoC Interconnect Network………........37
3.1.4.1 Static Network……………………………........37
3.1.4.2 Dynamic Network………………………...........37
3.2 Routers (communication controllers)………….....38
3.2.1 OSI Behaviour Model…………..………….........38
3.2.2 Router Model………………………………..........39
3.2.2.1 Related Router Model……………………........40
3.2.2.1 Proposed Router Model…………………….......41
3.2.2.1.1 General router model……………………......42
3.2.2.1.2 Specific Router Model………………….......50
3.2.3 Router Parameters………. ……..………….......54
3.2.4 Static Switch………………………………….......55
3.2.4.1 Switch Controller (SC)……………………......56
3.2.4.2 Switch Allocator (SA)…………………….......57
3.2.4.3 Switch Fabric……………………………….......57
3.2.4.4 Proposed Static Switch Processor…………....58
3.2.4.5 Static Network Flow Control — Static Ordering..58
3.2.5 Dynamic Switch…………………………............59
3.2.5.1 Switch Controller……………………….…......60
3.2.5.2 Switch Allocator…………………………........60
3.2.5.3 Proposed Dynamic Switch Processor…….......61
3.2.5.5 Dynamic network flow control……………….....62
3.3 Network Interface……………………...…......62
Chapter 4 aNoC Computation Components and Memory System
4.1 aNoC computation components……………….........65
4.1.1 Basic Model………...………………........65
4.1.2 Reconfigurable Structure of the Tile Processor.67
4.1.3 Proposed Tile Processor Structure……...……...67
4.1.3.1 Registers of the tile processor……..…..……68
4.1.3.1.1 Network registers…………..………...……...68
4.1.3.1.2 Special purpose registers……....…...…….69
4.1.3.2 Energy Efficiency Techniques……….……...….70
4.1.4 Threading Mechanism — Featherweight thread……70
4.1.4.1 Fast thread switching — Block Multithreading…71
4.1.4.2 Scheduling for Featherweight Threads……...…..72
4.2 aNoC Memory System……………...……...........72
4.2.1 DMA mode……………...…….............74
4.2.2 Memory Model and Synchronization……………….74
4.2.3 Latency Tolerance of the aNoC Memory………….74
Chapter 5 aNoC Application Interface
5.1 Computation Application Interface (CPAI)……...78
5.2 Communication Application Interface (CMAI)…....79
5.2.1 Physical Layer of the CMAI……………………….81
5.2.2 Network Layer of the CMAI………………….…..82
5.2.3 Transport (User) Layer of the CMAI………....84
5.2.3.1 Message Injection Instructions…………....84
5.2.3.2 Message Extraction Instructions....……..85
5.2.3.3 User-Level Atomicity and the Execution Model...86
5.2.3.4 Implementation of Message Injection/Extraction Instructions….87
5.2.3.4.1 Implementation of Message Injection Interfaces.88
5.2.3.4.2 Implementation of Message Extraction Instruction.……95
5.2.3.5 The User-Level Atomicity Mechanism…….101
Chapter 6 aNoC Integration and Application Mapping
6.1 aNoC platform integration…………........111
6.2 Application Mapping………….....116
6.2.1 Application Mapping Example…………..118
Chapter 7 aNoC Conclusion.....122
Reference……………………...........123

[Agarwal 98] Agarwal, A., Moritz, C. A., & Yeung D. "Exploring Optimal Cost-Performance Designs for Raw Microprocessors". Proceedings of the International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM98, April 1998.
[Agrawal 99]A. Agrawal, “Raw Computation,” Scientific Am., Aug. 1999, pp. 60-63.
[Alberto 00] A. Sangiovanni-Vincentelli et al., “Formal Models for Communication-based Design”. Proceedings of the 11-th International Conference on Concurrency Theory, Concur ''00, August 2000.
[Alberto 01] Alberto Sangiovanni Vincentelli with Larry Pileggi. “White Paper on Platform-based Design”. DRAFT, December 7th, 2001.
[Anant 99] Anant Agarwal, Ricardo Bianchini, David Chaiken, Frederic t. Chong, Kirk l. Johnson, David Kranz, John d. Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, and Donald yeung. “The MIT Alewife Machine”. PROCEEDINGS OF THE IEEE, VOL. 87, NO. 3, MARCH 1999.
[Andrew 93] Andrew A. Chien, “A Cost and Speed Model for k-ary ncube Wormhole Routers”, In Proceedings of Hot Interconnects, Palo Alto, August 1993.
[Babb 97] J. Babb, M. Frank, V. Lee, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, and A. Agarwal. The raw benchmark suite: Computation structures for general purpose computing. In IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, Apr. 1997.
[Barua 99] Barua, R., Lee, W., Amarasinghe S., Agarwal a., "Maps: A Compiler-Managed Memory System for Raw Machines" To appear in the Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines ''99 (FCCM ''99), Napa Valley, CA, April 1999.
[Chen 92] D. C. Chen and J. M. Rabaey, "A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths", IEEE Journal of Solid-State Circuits, 27, no. 12, pp. 1895-1904, December 1992.
[Cierto] Cierto VCC, Cadence Design Systems. http://www.cadence.com/technology/hwsw/ciertovcc/
[Clos 53] C. Clos, "A Study of Nonblocking Switching Networks", Bell System Technical Journal, vol. 32, no. 2, pp. 406-424, 1953.
[Dally 86] W. J. Dally, C. L. Seitz, "The torus routing chip," Journal of Distributed Computing, vol. 1, no. 3, pp. 187--196, 1986.
[Dally 87] W. Dally, C. Seitz, "Deadlock-free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computers, vol. C-36, no. 5, pp. 547-553, May 1987.
[Dally 91] Dally, W. J., “Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks”, IEEE Transactions on Computers, Sept. 1991.
[Dally 92] W. J. Dally, "Virtual-Channel Flow Control", IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, March 1992.
[Guerrier 00] P. Guerrier and A. Grenier, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. IEEE Design Automation and Test in Europe (DATE 2000), IEEE Press, Piscataway, N.J., 2000, pp. 250-256.
[Ho 01] R. Ho, K. Mai, and M. Horowitz, “The Future of Wires,” Proc. the IEEE, Apr. 2001, pp. 490-504.
[Hoare 85] C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall International Series in Computer Science, 1985.
[Horowitz 93] M. Horowitz and K. Keutzer. ''Hardware-software co-design’’. In SASIMI’93, October 1993, pp. 5-14.
[Hutchinson 91] N. C. Hutchinson and L. L. Peterson. ”The x-kernel: an architecture for implementing network protocols”. IEEE Transactions on Software Engineering, Vol. 17, No. 1, pp. 64-76, January 1991.
[Jian 00] Jian Liang, Sriram Swaminathan, and Russell Tessier. “aSOC: A Scalable, Single-Chip Communications Architecture”. Proc. of the IEEE Int. Conf. on Parallel Architectures and Compilation Techniques, PA. October 2000.
[Jose 94] Jose Duato and Pedro Lopez, “Performance Evaluation of Adaptive Routing Algorithms for k-ary n-cubes”, In Proceedings of Parallel Computer Routing and Communication Workshop, May 1994.
[Kevin 93] Kevin Bolding et. al., “The Chaos Router Chip: Design and Implementation of an Adaptive Router”, In Proceedings of IFIP Conference on VLSI, September 1993.
[Kohler 00] E. Kohler, R. Morris, B. Chen, J. Jannotti, F. Kaashoek. ”The Click Modular Router”. ACM Transactions on Computer Systems, Vol. 18, No. 3, August 2000, pp. 263-397.
[Kurt 99] K. Keutzer, "Chip Level Assembly (and not Integration of Synthesis and Physical) is the Key to DSM Design", Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (Tau''99), Monterey, CA, USA, March 1999.
[Kurt 00] Kurt Keutzer et al. ”System-Level Design: Orthogonalization of Concerns and Platform-Based Design”. IEEE Transactions on Computer-Aided Design. Vol. 19, No. 12. December 2000.
[Leijten 98] J. Leijten et al., "Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor", Proceedings of the 1998 DATE Conference, Paris, France, March 1998.
[Luca 01] Luca Benini and Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computers, January 2002, pp. 70-78. 2001.
[Miller 97] D. R. Miller and W. A. Najjar, “Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers”, In Proceedings of International Conference on Parallel Architectures and Compilation Techniques, San Francisco, November 1997.
[Passerone 98] R. Passerone et al., “Automatic Synthesis of Interfaces Between Incompatible Protocols”, Proceedings of the 31st Design Automation Conference, San Francisco, CA, pp. 8-13, June 1998.
[Patrick 01] Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh. A Quick Safari Through the Reconfiguration Jungle. Annual ACM IEEE Design Automation Conference, 2001 , Las Vegas, Nevada, United States.
[Peh 00] Li-Shiuan Peh, William J. Dally, “Flit-Reservation Flow Control”, In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. pp. 73-84.
[Peh 01]Li-Shiuan Peh and William J. Dally, A Delay Model and Speculative Architecture for Pipelined Routers, In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan. 22-24, 2001, Monterrey, Mexico, pp. 255-266.
[Sgroi 01] M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli. “Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design”. A. Sangiovanni-Vincentelli, Proceedings of the 38th Design Automation Conference, June, 2001.
[Silva 00] J. Silva et al. “Wireless protocols design: challenges and opportunities,” Proceedings of Int. Workshop on Hardware/Software Codesign, May 2000.
[Sonicsinc] http://www.sonicsinc.com
[Sproull 91] R. F. Sproull and I. E. Sutherland, “Logical Effort: Designing for Speed on the Back of an Envelope”, IEEE Advanced Research in VLSI, C. Sequin (editor), MIT Press, 1991.
[Sutherland 99] Ivan Sutherland, Bob Sproull and David Harris, “Logical Effort: Designing Fast CMOS Circuits”, Morgan Kaufman Publishers, 1999.
[Sylvester 00] D. Sylvester and K. Keutzer, “A Global Wiring Paradigm for Deep Submicron Design,” IEEE Trans. CAD/ICAS, Feb. 2000, pp. 242-252.
[Thesis 00]T. Theis, “The Future of Interconnection Technology,” IBM J. Research and Development, May 2000, pp. 379-390.
[VSIA 99] Virtual Socket Interface Alliance, "On-Chip Bus Attributes" and "Virtual Component Interface — Draft Specification, v. 2.0.4", http://www.vsia.com, September 1999 (document access may be limited to members only).
[Walrand 00] J. Walrand and P. Varaiya, High-Performance Communication Networks, Morgan Kaufmann, San Francisco, 2000.
[Zhang 99] Zhang, H., Wan, M., George, V., Rabaey, J. “Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs”. Proceedings of the WVLSI , Orlando, FL, USA, April 1999.
[Zhang 00] H. Zhang, et al. “A 1-V hererogeneous reconfigurable DSP IC for wireless baseband digital signal processing,” IEEE J. Solid State Circuits, vol. 35, Nov. 2000, pp. 1697-1704.