臺灣博碩士論文加值系統

本篇論文描述一個具有內插技術之高速八位元互補金氧半快閃式類比數位轉換器。在本設計中所使用之無空轉時間之自動歸零技術是一個有效的方法來降低由於製程變動所產生的偏移誤差。開關式前置放大器用來避免傳統自動歸零所需之非重疊控制信號與消除高速自動歸零對輸入端造成的干擾。除此之外，相對於最近所發表之自動歸零之快閃式類比數位轉換器所需多相位時脈，此電路架構有單一相位控制的優點並避免了同步問題。電阻式的內插技術在整體類比數位轉換器可以有效降低輸入負載、前置放大器數目以及差值非線性誤差。為了消除在內插點上前置放大器到拴鎖器的延遲時間不同這個問題，增加額外串聯阻抗將拴鎖器之間的延遲等效化。具有連線灰階編碼之編碼器在此被使用來降低比較器亞穩態所造成之脈衝誤差與在熱碼的氣泡誤差。
這個類比數位轉換器實現是採用0.25μm，1P5M互補金氧半混合信號製程，面積為1.4×1.73mm2。佈局後的模擬結果證實此類比數位轉換器在輸入信號為30MHz，操作頻率為200MHz時，具有7.5位元的有效解析度。整個晶片在2.5伏特的供應電壓下，消耗430mW的功率。與目前全世界已發表最好的CMOS八位元每秒二百萬次取樣快閃式類比數位轉換器比較，此設計具有較小面積、供應電壓及功率。

This thesis describes an high-speed 8-bit CMOS flash ADC with 8X interpolation. In this design, autozeroing technique without idle time is an effective way to suppress offset error due to process variation. Switching preamplifiers are provided to avoid using non-overlap control signals required by conventional autozeroing ADCs and to eliminate the interference, caused by the high-speed autozeroing operation, at input nodes. Besides, this circuit architecture has the merit of a single-phase control to avoid synchronous problems since multi-phase clocks are necessary for recent published flash ADCs with autozero. Resistive interpolation technique can efficiently reduce input loading, preamplifier number and differential nonlinearity (DNL) error in the ADC. Encoder with wired Gray coding is used to suppress glitch errors caused by the comparator metastability and bubble errors in the thermometer code.
The ADC is fabricated in 0.25μm 1P5M CMOS technology and occupies an area of 1.4x1.73mm2. Post-layout simulation demonstrates that the ADC can digitize an input 30MHz with 7.5 effective bits at 200Msample/s. The ADC consumes 430mW from 2.5V power supply. Compared with the best CMOS 8-bit 200MSPS flash A/D converter in the world, this design is with smaller area, lower supply voltage and less power.

1. Introduction ............................................1
1.1 Motivation .............................................1
1.2 Thesis organization ....................................2
2. Overview of High-Speed ADC Architecture .................3
2.1 Flash A/D Converter ....................................3
2.2 Two-Step and Subrange A/D Converter ....................5
2.3 Folding A/D Converter ..................................6
2.4 Pipelined A/D Converter ................................7
2.5 Time-Interleaved A/D Converter .........................9
3. Error Analysis and Design Technique for Flash ADC ...... 11
3.1 Offset .................................................11
3.2 Metastability and Hystersis ............................16
3.3 Signal-Dependent Comparator Delay ......................18
3.4 Jitter .................................................21
3.5 Autozeroing Technique ..................................23
3.5.1 Autozeroing Principle ..................23
3.5.2 Autozeroing Topology ...................24
3.5.3 Modified Autozeroing ...................26
3.6 Averaging Technique .....................................27
3.6.1 Offset Reduction with Averaging Network ......................................29
3.6.2 Mathematical Derivation of Averaging Network ......................................31
3.7 Interpolation Technique ................................34
4. Circuit Implementation ..................................38
4.1 Architecture Design of 8-Bit Flash ADC ..................38
4.2 Reference Ladder .......................................39
4.3 Comparator Circuit .....................................42
4.3.1 Circuit Topology and Consideration ...............................43
4.3.2 Input Stage of Comparator ..................................43
4.3.3 Preamplifiers and First Latch Circuits ....................................45
4.3.4 Second Latch and S-R Latch Circuits ....................................46
4.4 Resistive Interpolation ................................48
4.5 Digital Encoder ......................................52
4.5.1 Considerations of Digital Encoder ......................................53
4.5.2 Implementation of Digital Encoder ......................................53
4.6 Clock Generator ........................................54
5. Layout and Results ......................................56
5.1 Floor Plan and Layout Considerations ...................56
5.2 Simulation Results .....................................58
5.3 Measurement Issues .....................................60
5.3.1 Measurement Setup ....................60
5.3.2 PCB Fabrication ......................61
5.4 Experimental Results ...................................61
6. Conclusion and Future Work ..............................62
References .................................................64

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