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研究生:陳世泫
研究生(外文):Shih-Hsuan Chen
論文名稱:鎖相迴路應用於頻率合成器之研究
論文名稱(外文):Phase Locked Loop Based Frequency Synthesizer Study
指導教授:盧志文盧志文引用關係
指導教授(外文):Chih-Wen Lu
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:125
中文關鍵詞:鎖相迴路頻率合成器相位頻率偵測器充電幫浦迴路濾波器電壓控制振盪器除頻器
外文關鍵詞:phased locked loop (PLL)frequency synthesizerphase/frequency detectorcharge pumploop filtervoltage-controlled oscillatordivider
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中文摘要
本論文鎖相迴路應用於頻率合成器(PLL based frequency synthesizer)之研究,係針對頻率合成器各子系統電路如相位頻率偵測器(phase/frequency detector)、充電幫浦(charge-pump)、迴路濾波器(loop filter)、電壓控制振盪器(voltage-controlled oscillator)與除頻器(divider)等,作電路特性、系統影響與電路架構的比較。
頻率合成器設計先以數學軟體MATLAB的SIMULINK工具和程式撰寫的方式對系統作行為模式的分析,再採用TSMC 0.35μm 1P4M 3.3V CMOS製程參數去做電路模擬。應用二種全差動延遲單元的電壓控制振盪器作電路模擬及電路特性和效能的分析。運用這二種電壓控制振盪器設計頻率合成器,並比較其特性與效能。
以最高操作頻率在400MHz的頻率合成器,採用TSMC 0.35μm 1P4M 3.3V CMOS製程去製作。包含其他測試電路與pads晶片面積為1.428㎜ × 1.428㎜,消耗功率為18.01 mW(模擬值)。
ABSTRACT
The research of this thesis, “Phase Locked Loop based Frequency Synthesizer,” is focused on each subsystem circuit of the frequency synthesizer, such as the phase/frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the divider. The comparison of the characteristics between the subsystems has been done.
To design the frequency synthesizer, the behavior of the system is analyzed by using the mathematics tool, SIMULINK of MATLAB. The schematic of the circuit is simulated by using HSPICE with the parameters of TSMC 0.35μm 1P4M CMOS process model. Two kinds of voltage-controlled oscillators, which are consisted by fully differential delay cells, are used to simulate the performance of the frequency synthesizer.
The frequency synthesizer is demonstrated in TSMC 0.35μm 1P4M CMOS technology. The simulated results show that the maximum operation frequency is 400 MHz and the power consumption is 18 mW. The chip area including the test circuit and pads is 1.428 mm × 1.428 mm.
Keywords: phased locked loop (PLL), frequency synthesizer, phase/frequency detector, charge pump, loop filter, voltage-controlled oscillator, divider.
目 錄
中文摘要 Ⅰ
英文摘要 II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 XI
第一章 緒論 1
1-1研究動機 1
1-2頻率合成器架構 2
1-3論文架構及研究方法 4
第二章 鎖相迴路相關簡介與頻率合成器子系統介紹 6
2-1 簡介 6
2-2鎖相迴路基本操作原理與發展型態 7
2-2-1 線性鎖相迴路 8
2-2-2 數位鎖相迴路 10
2-2-3 全數位鎖相迴路 11
2-2-4 軟體(程式)鎖相迴路 12
2-3頻率合成器子系統簡介 14
2-3-1 相位頻率偵測器 14
2-3-2 充電幫浦與迴路濾波器 15
2-3-3 電壓控制振盪器 17
2-3-4 除頻器 18
第三章 頻率合成器各子系統特性分析與電路架構分析 19
3-1 相位頻率偵測器 19
3-1-1 傳統與動態邏輯型式之相位頻率偵測器比較 20
3-1-2 相位頻率偵測器之性能指標 24
3-2 迴路濾波器 28
3-2-1 迴路濾波器對系統影響 28
3-3 充電幫浦 33
3-3-1 充電幫浦的設計考量與系統影響 33
3-3-2 各種充電幫浦電路架構介紹與比較 35
3-4 電壓控制振盪器 46
3-4-1 環形振盪器 47
3-4-2 設計電壓控制振盪器的重要效能參數介紹 51
3-4-3 電壓控制振盪器雜訊來源 54
3-4-4 各類型Delay buffer cell比較 60
3-4-5 具有全差動對稱性負載延遲的振盪電路 62
3-4-5-1 對稱性負載 66
3-4-5-2 延遲單元偏壓電路 69
3-5 除頻器電路 73
3-5-1 前置除頻器 73
第四章 頻率合成器相關電路設計與模擬結果 80
4-1 頻率合成器之系統操作參數 80
4-1-1 相位雜訊 80
4-1-2 突波 82
4-1-3 快速切換動作 83
4-1-4 頻率解析度 84
4-1-5 應用的電源、功率消耗與面積大小 85
4-2 頻率合成器之數學模型分析 85
4-2-1 相位頻率偵測器與充電幫浦 86
4-2-2 迴路濾波器 87
4-2-3 電壓控制振盪器 89
4-2-4 除頻器 90
4-2-5 頻率合成器閉迴路分析 90
4-2-6 頻率合成器行為模式模擬 94
4-3 整數型頻率合成器:子系統電路設計與電路模擬結果 97
4-3-1 相位頻率偵測器 97
4-3-2 充電幫浦 100
4-3-3 迴路濾波器 100
4-3-4 電壓控制振盪器 103
4-3-5 除頻器 110
4-3-6 頻率合成器電路模擬結果 112
第五章 結論與未來工作 115
5-1 結論 115
5-2 未來工作 116
參考文獻 118
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