臺灣博碩士論文加值系統

單一電晶體鐵電記憶體因其較小的元件面積和非破壞性讀寫的操作方式等優點而成為下一世代的鐵電記憶體。在本研究中，鋯鈦酸鉛和鑭取代鈦酸鉍這兩組鐵電薄膜同樣地被證實是可以整合在具有金屬-鐵電薄膜-絕緣層-半導體 (MFIS) 這樣疊層閘極結構的單一電晶體記憶體中，另外在這種MFIS的閘極電容中，氧化鋁因其比具有相同等效氧化層厚度的氧化矽較高的介電常數和較低的漏電流而被視為適當的絕緣層材料來使用。首先，比起傳統的MFM電容而言，MFIS閘極電容被證明不但具有類似的記憶效應而且其漏電流也比MFM電容來得低；在鋯鈦酸鉛/氧化鋁/矽基板的MFIS電容中，因為發現在氧化鋁基板上成長富鈦成分的鋯鈦酸鉛比起富鋯成分的鋯鈦酸鉛具有較低的的鈣鈦礦轉換溫度，所以鈦酸鉛緩衝層被用來抑止在鋯鈦酸鉛/氧化鋁/矽基板的MFIS電容中Pyrochlore相的生成，另外，和富鋯鋯鈦酸鉛/鈦酸鉛/氧化鋁/矽基板電容因電荷注入所得到的記憶效應來做比較，富鈦鋯鈦酸鉛/鈦酸鉛/氧化鋁/矽基板電容所得到的是鐵電式的記憶效應；在鑭取代鈦酸鉍/氧化鋁/矽基板電容中，和退火溫度相關的效應被研究後因而發現由較高溫度退火得到的鑭取代鈦酸鉍/氧化鋁/矽基板電容會有較大記憶窗和較低的漏電流，經由進一步地探討其界面反應後可以發現，氧化鋁絕緣層與鐵電薄膜和矽基板在退火時的反應應該是電容低漏電的主因，另外，較高溫度退火後所得到有較大晶粒的鑭取代鈦酸鉍鐵電薄膜亦是造成較大的記憶窗的原因之一；最後，單一電晶體記憶體元件的相關關鍵製程根據在之前在MFIS電容特性上的研究結果而被發展，經過實際上單一電晶體記憶體元件的記憶特性量測後可以發現，本研究所發展的鐵電薄膜製程不但可以在MFIS電容上具有優異的記憶特性，此外配合相關的半導體製程，本研究所發展的MFIS疊層閘極結構更是被證實可以進一步地應用在真實的記憶元件上。

Among many kinds of ferroelectric random access memories (FeRAMs), one-transistor (1T) ferroelectric MOSFET (FeMOSFET) type memory is very attractive due to the same small 1T cell and nondestructive read-out (NDRO) operation. Pb(ZrxTi1-x)O3 (PZT) and Bi3.25La0.75Ti3O12 (BLT) ferroelectric thin films have been integrated in 1T memory with metal-ferroelectric-insulator-semiconductor (MFIS) gate structure. Al2O3 was found to be a suitable insulator material in these MFIS capacitors due to the higher dielectric constant and lower leakage current than those of SiO2 with the same equivalent oxide thickness (EOT). Besides, the MFIS capacitors were demonstrated to have similar memory effect and lower leakage current in comparison with the metal-ferroelectric-metal (MFM) capacitors. In PZT/Al2O3/Si capacitors, the usage of PbTiO3 (PTO) seeding layer was found to be able to inhibit the formation of pyrochlore phase because Ti-rich PZT films have lower perovskite transformation temperatures than those of Zr-rich PZT films on Al2O3 buffered Si. Besides, the memory effect of Ti-rich PZT/PTO/Al2O3/Si capacitors was attributed to the ferroelectricity in contrast to those of Zr-rich PZT capacitors derived from charge injection. For BLT/Al2O3/Si capacitors, the effects of annealing temperature were investigated and the capacitors annealed in higher temperatures would have larger memory window and lower leakage current. Furthermore, the interface reaction was studied so that the lower leakage current of capacitors was suggested to be the result of the high temperature reaction of insulator with ferroelectric and Si though the larger grain size of BLT films annealed in the higher temperatures would correspond to the larger memory window of capacitors. The related processing for 1T memory devices were developed in this thesis and the device characteristics were also demonstrated.

ABSTRACT (Chinese) i
ABSTRACT ii
DEDICATION iii
ACKNOWLEDGEMENT iv
CONTENTS v
LIST OF TABLES x
LIST OF FIGURES xi
CHAPTER 1 1
Introduction 1
1.1. High-k gate dielectric materials 1
1.2. Ferroelectric materials 4
1.2.1. Simple perovskite PZT 4
1.2.2. Bismuth layer-structured ferroelectric materials 5
1.3. FeRAMs progress 6
1.3.1. Nondestructive readout (NDRO) one transistor memory 6
1.3.2. Metal-ferroelectric-insulator-semiconductor (MFIS) structure 7
1.4. Literature review of MFIS structure 8
1.4.1. MFIS structure with PZT as the ferroelectric layer 9
1.4.2. MFIS structure with bismuth layered structure ferroelectric as the ferroelectric layer 11
CHAPTER 2 27
Experimental 27
2.1. Substrate preparation for different capacitor structures 27
2.1.1. Preparation of Pt/Ti/SiO2/Si substrates for the MIM capacitor 27
2.1.2. Preparation of Al2O3/Si substrates for the MFIS capacitor 27
2.2. Fabrication method of ferroelectric thin films 27
2.2.1 Chemical-solution-derived PZT films 27
2.2.1 Chemical-solution-derived BLT films 28
2.3. Preparation of MFM and MFIS capacitors 29
2.3.1. Preparation of MFM capacitors 29
2.3.1. Preparation of MFIS capacitors 29
2.4. Characteristic measurements 29
2.4.1. Measurement of capacitance-voltage (C-V) characteristics 29
2.4.2. Measurement of current density-voltage (J-V) characteristics 30
2.4.3. Other analytical instruments 30
CHAPTER 3 37
Ferroelectric characteristics of oriented Pb(Zr1-xTix)O3 films 37
3.1. Introduction 37
3.2. Experimental procedure 38
3.2.1. Preparation of stock solution and fabrication of thin film 38
3.2.2 Characterization and property measurement 39
3.3. Results and discussion 39
3.3.1 Structure analysis 39
3.3.2. Hysteresis loop 40
3.3.3. Fatigue property 42
3.4. Conclusions 45
CHAPTER 4 54
Electrical and structural characteristics of PbTiO3 thin films with ultrathin Al2O3 buffer layers 54
4.1. Introduction 54
4.2. Experimental procedure 55
4.3. Results and discussion 56
4.4. Conclusions 58
CHAPTER 5 64
Characteristics of Pb(Zr0.53Ti0.47)O3 on metal and Al2O3/Si substrates 64
5.1. Introduction 64
5.2. Experimental procedure 65
5.3. Results and discussion 66
5.4. Conclusions 69
CHAPTER 6 75
Effect of Zr/Ti ratios on the characteristics of Pb(ZrxTi1-x)O3 thin films on Al2O3-buffered Si 75
6.1. Introduction 75
6.2. Experimental procedure 76
6.2.1. PZT stock solution synthesis and thin film deposition 76
6.2.2. Preparation of Al2O3/Si and PTO/Al2O3/Si substrates 76
6.2.3. Film characterization 77
6.3. Results and discussion 77
6.3.1. Phase transformation of single-layer PZT on Al2O3/Si 77
6.3.2. Comparison of phase evolution of 650oC-annealed PZT on Al2O3/Si and those on PTO/Al2O3/Si 79
6.3.3. Electrical properties of PZT/PTO/Al2O3/Si capacitors 80
6.4. Conclusions 82
CHAPTER 7 98
Bi3.25La0.75Ti3O12 thin films on ultrathin Al2O3 buffered Si for ferroelectric memory application 98
7.1. Introduction 98
7.2. Experimental procedure 99
7.3. Results and discussion 100
7.4. Conclusions 102
CHAPTER 8 108
Effect of annealing temperature on physical and electrical properties of Bi3.25La0.75Ti3O12 thin films on Al2O3-buffered Si 108
8.1. Introduction 108
8.2. Experimental procedure 109
8.3. Results and discussion 109
8.4. Conclusions 111
CHAPTER 9 118
Role of the high temperature reaction of Al2O3 with Bi3.25La0.75Ti3O12 and Si in the metal-ferroelectric-insulator-semiconductor capacitors 118
9.1. Introduction 118
9.2. Experimental procedure 119
9.3. Results and discussion 120
9.4. Conclusions 123
CHAPTER 10 132
One-transistor PZT/Al2O3 and BLT/Al2O3 stacked gate memory 132
10.1. Introduction 132
10.2. Experimental procedure 132
10.3. Results and discussion 133
10.3.1 Composition dependent characteristics of PZT/Al2O3/Si 1T memory 133
10.3.2 Annealing temperature dependent characteristics of BLT/Al2O3/Si 1T memory 133
10.4. Conclusions 134
CHAPTER 11 139
Conclusions 139
11.1. One-transistor ferroelectric memory with Pb(ZrxTi1-x)O3 and Al2O3 as the ferroelectric and insulator layers 139
11.2. One-transistor ferroelectric memory with Bi3.25La0.75Ti3O12 and Al2O3 as the ferroelectric and insulator layers 139
REFERENCE 141
PUBLICATION 158

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