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研究生:蔡俊良
研究生(外文):Jiu-Liang Tsai
論文名稱:適用於DCS-1800無線通訊規格1.8GHz之互補式金氧半頻率合成器
論文名稱(外文):A Fully Integrated CMOS 1.8GHz Frequency Synthesizer for DCS-1800 Wireless Communication Systems
指導教授:吳重雨
指導教授(外文):Chung-Yu Wu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:91
語文別:英文
論文頁數:77
中文關鍵詞:頻率合成鎖相迴路低通濾波器
外文關鍵詞:frequency synthesisphase-locked loopsPLLlow pass filter
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本論文主要是在實現適用於DCS-1800 無線通訊規格之互補式金氧半頻率合成器,作為本地振盪產生器之用途。此電路中包含了壓控振盪器,預先除頻器,可程式計數器,相位頻率偵測器,電荷充放電電路,以及低通濾波器。另外,還包含了一個移位暫存器,作為輸入數位碼以提供通道選擇之用。在這個電路中,一個改良的主動式雙路徑低通濾波器將被提出。藉此技巧,可以將三階的低通濾波器整合到晶片上,而不需要外掛被動元件。整個電路原理和動作大致如下:
首先電路由壓控振盪產生一個射頻訊號。這個射頻訊號經由預先除頻器轉為低頻的數位訊號,再透過可程式計數器頻率降頻為Fdiv。然後用相位頻率偵測器去比較輸入參考頻率(fref)和Fdiv的相位差。這個相位差會透過電荷充放電轉成類比訊號,透過低通濾波器變成一個近似 dc 的類比連續信號。這個訊號可以用來控制壓控震盪器,把射頻訊號的頻率調高或調低。經由這樣的迴授機制,最後從壓控振盪器輸出的訊號頻率將是參考頻率 fref 的整數倍。把一個精準穩定的低頻訊號提升到不同的高頻頻段,完成了頻率合成的工作
整個電路是操作在 3.3伏特,以台灣積體電路公司零點三五微米互補式金氧半製程實現,壓控振盪器的中心頻率為 1.8 GHz,調頻範圍約為 477 MHz ( 26.5﹪),功率消耗約 12.3mW。整個頻率合成器消耗功率約為 40mW,晶片面積約是 1.6 mm x 0.8 mm,並送交由國科會晶片製造中心進行製作。最後予以量測。

This thesis is primary to implement a CMOS frequency synthesizer in DCS-1800 wireless application as a local oscillator. The circuit consists of a voltage-controlled oscillator (VCO), prescalar, programmable counter, phase frequency detector, charge pump circuit, and a low-pass filter. Besides, a shift register is also included for digital code inputs for which provides channel selection. In the circuit, an improved active dual-path loop filter is proposed. By this technique, a third-order loop filter can be integrated on chip without external passive components. Operational principles of all the circuit is as follows:
First, the voltage-controlled oscillator generates an radio-frequency (RF) signal. This RF signal frequency is down-converted to low frequency through prescalar. And again, the output frequency is down to lower frequency (Fdiv). After that, Phase Frequency Detector will detect the phase difference of the input reference frequency (Fref) and Fdiv. The phase difference becomes a successive dc-like analog signal by low pass filter. It will control the voltage-controlled oscillator, which tuning the RF signal up or down. Finally, the feeedback mechanism attains that the output frequency will be integral multiple of the reference frequency, fref. Frequency synthesis is achieved by making a precise low reference frequency, fref, up-converted to different high frequency band.
All the circuits are operated at 3.3V power supply, implemented with TSMC0351P4M CMOS process technology. Central frequency of the voltage-controlled oscillator is 1.8 GHz, tuning range is 477 MHz ( 26.5﹪), power dissipation is about 12.3mW. The whole synthesizer dissipates about 40 mW, die size is 1.6mm x 0.8mm. It chip is implemented by Chip Implementation Center. Finally, the chip is measured.

ABSTRACT (CHINESE)………………………………………..I
ABSTRACT (ENGLISH)………………………………………..III
CONTENTS…………………………………………………………V
TABLE CAPTIONS……………………………………………VIII
FIGURE CAPTIONS……………………………………………IX
CHPATER 1 Introduction
1.1 Background And Review 1
1.2 Mitivations 2
1.3 Organization Of This Thesis 3
CHPATER 2 An Improved Active Loop Filter
2.1 Trade-offs among the architectures 4
2.2 Passive Loop Filter 6
2.3 Dual-Path Loop Filter 7
2.4 Improvd Loop Filter 10
2.5 Behavioral Simulation and Designed Specifications 12
CHAPTER 3 The Principles of Frequency Synthesizers :Overall Synthesizer And Simulated Results
3.1 General Considerations 26
3.1.1 Phase Noise Definition 29
3.3.2 Spurious Tone Definition 30
3.2 Designed PLL Architecture
3.2.1 Voltage-Controlled Oscillator (VCO) 31
3.2.2 Prescalar 35
3.2.3 Phase/Frequency Detector (PFD) 43
3.2.4 Charge Pump/Loop Filter (CP/LP) 45
3.2.5 Pulse Swallow Counter 48
3.2.6 Shift Rigister and Pad buffer 53
3.3 Hspice Simulated Results 55
CHAPTER 4 Experimental Results
4.1 Layout Descriptions 58
4.2 Testing System Setup 60
4.3Experimental Results 61
CHPATER 5 Conclusions and Future Work
5.1 Conclusions 76
5.2 Future work 76
APPENDIX
Appendix (A) PLL Linear Noise Model Derivation
Appendix (B) Design formula of the proposed loop filter
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