臺灣博碩士論文加值系統

本篇論文主旨在設計一個具有高共模抑制能力之功率放大器及一個可應用於bluetooth規格之直接昇頻式射頻發射器。這兩個晶片皆是使用一標準點25微米1P5M 補式金氧半導體製程。在射頻發射器的晶片中，包含了正交相位調變器，四相位壓控振盪器及功率放大器。功率放大器的晶片可以在2.45GHz的頻率下提供21.03 dBm的輸出功率，同時有著28%的效率。在使用2.5V電源的情況下，功率放大器晶片之工作電流為179mA。由量測的結果可驗証，這個功率放大器的規格適合工作在短距離無線傳輸的應用上，而且可以符合Bluetooth class 1的輸出功率規格(20dBm)。在正交相位調變器中，電流的消耗僅只有25mA在一2.5V之電源下。因為使用了電流再使用的技術於正交相位調變器及四相位壓控振盪器，低功率消耗的射頻發射器得以實現。四相位壓控振盪器的可調頻率為132MHz，從2.353GHz到2.465GHz當控制電壓從1V變化至2.5V。因為調變器的負載電感電容的偏移，及當做功率放大器負載之螺旋形電感有著較低的品質因數，導致調變器有著一個很小的轉換增益。而量測到的發射器輸出功率為-9.15dBm，震盪器信號漏溢和鏡像信號比例分別為-4.6dBc及-31.7dBc。

A power amplifier with high common-mode rejection capability and a RF transmitter for Bluetooth applications are presented in this thesis. These two proposed chips are fabricated in a standard 0.25μm single-poly-five-metal CMOS process. In the transmitter chip, it consists of a quadrature modulator, a quadrature VCO, and a power amplifier. The power amplifier chip can provide up to 21.03dBm output power with 28% efficiency at 2.45GHz. The operation current of the fabricated power amplifier chip is 179mA from a 2.5V power supply voltage. Through measured results, the performance of the proposed CMOS RF power amplifier has been verified to be well suitable for short-range communication applications and can meet Bluetooth output power level class 1(20dBm). The current consumption of proposed modulator is only 25mA from a 2.5V power supply voltage. The transmitter chip with low-power-dissipation is enabled by the current reuse technique used among quadrature modulator and quadrature VCO. The 132MHz tuning range of the realized quadrature VCO can be varied from 2.353GHz to 2.465GHz while controlled voltage changes between 1V and 2.5V. Due to the variation of the LC loads of the modulator and the lower quality factor of the spiral inductor as the load of power amplifier, changes the center frequency of each stage amplifier and results in a small conversion gain of the modulator. The measured output power of the transmitter is —9.19dBm,and the measured LO leakage, image ratio of the modulated signal at the output of transmitter is —4.6dBc, -31.7dBc, respectively.

Chapter1 INTRODUCTION 1
1.1 Background 1
1.2 Review on CMOS RF Transmitter Circuits 2
1.3 Motivation 5
1.4 Organization of This Thesis 6
Chapter2 THE DESIGN OF CMOS RF POWER AMPLIFIER 8
2.1 Design consideration 8
2.2 Power Amplifier Design Concept 9
2.3 Circuit Realization 13
2.3.1 Power Amplifier structure 13
2.3.2 New Design: a circuit which has common-mode rejection capability 14
2.4 Comparison : Power amplifier with common-mode rejection capability Versus Power amplifier without common-mode rejection capability 21
2.5 Simulation Results 28
Chapter3 THE DESIGN OF A 2.4-GHZ CMOS RF TRANSMITTER 33
3.1 Design Consideration 33
3.2 Direct-Conversion Quadrature Modulator 37
3.2.1 Operational Principle 37
3.2.2 Circuit Realization 40
3.3 Merged Quadrature Voltage Controlled Oscillator 45
3.4 Complete Transmitter Circuits Design 49
3.5 Simulation Results 50
Chapter4 EXPERIMENTAL RESULTS 55
4.1 Chip Layout Descriptions 55
4.2 Measurement Setup 60
4.3 Experimental Results 65
Chapter5 CONCLUSIONS AND FUTURE WORKS…. 84
5.1 Conclusions 84
5.2 Future Works 85
REFERENCE……………………………………86

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