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研究生:鄒年凱
研究生(外文):Niain-Kai Zous
論文名稱:積體電路元件中因氧化層漏電所引發可靠性問題的探討
論文名稱(外文):investigation of oxide leakage current related reliability issues in VLSI devices
指導教授:汪大暉
指導教授(外文):Tahui Wang
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:91
語文別:英文
論文頁數:150
中文關鍵詞:漏電氧化層穿隧氧化層快閃式記憶體
外文關鍵詞:leakage currentoxidetunnel oxideflash EEPROM
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在本論文中,首先將探討在穿隧氧化層中因熱電洞注入而產生的暫態漏電流。氧化層中正電荷的存在會幫助電子穿隧通過氧化層,吾人發現此為造成加壓後閘極漏電流形成的主因,而其暫態效應則歸因於正電荷穿隧脫離氧化層所造成此漏電路徑的消失。此種閘極漏電流與正電荷穿隧脫離氧化層所造成的基極電流其與時間的關係皆可用t-n來描述,而其n值對兩者而言分別為0.7與1。吾人並推導出解析公式來描述其時變性,而根據此公式,其n值與電子和電洞的質量、穿隧能障的大小相關。在實驗方面,吾人驗證了此閘極暫態電流與基極漏電流是呈正相關的,因此基極漏電流可作為評估閘極暫態漏電流的指標。藉由適當的熱電子注射,可大幅消減此一因氧化層正電荷存在所造成的閘極漏電流。
基於上述觀察所得,吾人重新檢視在穿隧氧化層中因Fowler-Nordheim (FN)加壓所形成的漏電流的機制與特性。由於FN所產生的正電荷通常會累積在氧化層中接近陽極處,因此在加壓和量測極性相反時,吾人可以觀測到較大而顯著的閘極暫態漏電流。在-FN的加壓與正偏壓的量測下,基極與閘極暫態漏電的正相關性,再一次的被驗證。而在因+FN加壓所形成的漏電中,吾人發現其穩態部分,隨加壓時間,會呈現先上升後下降的轉折特性。此一現象與+FN加壓時,閘極所反映出來的加壓電流特性相似,也隱含了此穩態漏電流與氧化層中正電荷的產生具有關聯。綜合來說,-FN加壓所導致的暫態漏電流與+FN所引發的穩態漏電流皆與正電荷的形成相關。
為能更進一步了解氧化層暫態漏電流在快閃式記億元件中因擾動所產生的臨界電壓飄移現象裡,所扮演的角色,吾人提出一數位模擬方法來準確的評估閘極和基極漏電流與電場和時間的關係,並根據此模型解釋在快閃式記億元件上所觀測到臨界電壓擾動的時變性。另外吾人發現正電荷在氧化層中形成的位置,會隨著加壓方式而有所不同,並對漏電流的大小產生很大的影響。而在Vs=3V時,此漏電流是最小的。此漏電流的主導機制會隨著氧化層厚度而有所轉變,根據吾人的實驗,當氧化層厚度從100Å下降到45Å時,其主導機制也會由正電荷所引發的電子穿隧電流漸漸變成由中性缺陷所幫助的漏電流。在漏電流的防治上,除前述電性中和法外,使用DDD結構或是利用NO來強化氧化層,皆可降低漏電流。
在超薄氧化層中,電荷幫浦法的準確性及適用性因漏電流的存在而備受質疑。因此根據基極漏電流形成的原因,吾人評估在使用電荷幫浦法時,其閘極電壓的可用範圍,以降低漏電流對此方法所產生的影響。在適當選取加壓範圍後,即使氧化層向下縮減到1.6nm,電荷幫浦法仍是一種觀測界面缺陷的好方法。而此範圍的大小,則取決於氧化層的厚度、閘極的長短與量測時所使用的頻率。
而在氧化層軟性崩潰上,吾人發現在崩潰後,元件在負偏壓量測下,所觀測到的基極漏電流與崩潰位置有很強烈的關係。假設此崩潰點發生在通道之內,所量測到的基極漏電流,大部份為閘極入射電子在基極中與電洞中和所產生的電流。而另一方面,若崩潰點是在靠近源極或汲極處,則因閘極電場會穿刺進入基極,會在源極或汲極處引發能帶對能帶間的穿隧電流。基於對此漏電流機制的了解,吾人提出一藉由基極電流的變化,來觀測崩潰位置的方法。

The transient behavior of hot hole stress induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. Our study shows that both SILC and stress induced substrate current have power law time-dependence t-n with the power factor n about 0.7 and 1, respectively. An analytical model is provided and the power factor n is dependent on both effective electron and hole tunneling barrier heights and their tunneling masses. A correlation between SILC and stress induced substrate current is observed. Stress induced low-field Ib can therefore be used as an effective monitor for PCAT effect in SILC. By using an appropriate hot electron injection technique, the PCAT current can be greatly reduced.
Based on this knowledge, the mechanisms and characteristics of FN SILC in tunnel oxides are re-examined. A larger SILC and a more significant transient effect is observed with opposite stress and measurement polarities due to the positive oxide charges generated by FN stress are usually trapped in the anode side. A correlation between —FN SILC and the substrate current is obtained again. The DC component of +FN SILC exhibits a turn around feature that is similar to the +FN stress gate current. The transient component of -FN SILC and the DC component of +FN SILC are attributed to positive oxide charge assisted tunneling current.
Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. In addition, we found that the +Qox position varies with erase stress bias and has a large effect on SILC. The Ib and SILC are found to be smallest around Vs=3V. The dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100Å to 53Å, the dominant SILC mechanism is found to change from PCAT to neutral trap assisted tunneling. Finally, the DDD structure and nitrided oxides are suggested to reduce the SILC transients.
The accuracy and validity of charge pumping (CP) method is questionable in ultra-thin gate oxide MOSFET’s due to the increase of the direct tunneling currents at low gate biases. A gate pulsing window for the CP technique is proposed to reduce the influence of this parasitic leakage current effect. Within the window, the CP method is still an excellent tool to measure the average interface trap density. On the other hand, the values of substrate currents must be taken into consideration while the gate pulsing bias is outside the window. Moreover, the range of this window strongly depends on the gate oxide thickness, the channel length and the gate pulsing frequency.
For the first time, we report the strong location dependence of substrate current after soft-breakdown under gate injection. The substrate current contributed by the channel recombination is positive and will increase abruptly if a soft breakdown path is located within the channel region. On the other hand, this substrate current turns out to be negative and larger while the soft breakdown is located within the gate-to-source (drain) overlap region. In this latter case, the increment of negative substrate current after soft breakdown is probably due to the band-to-band current induced by gate voltage penetration into the edge. This finding facilitates the detection of the location of SBD events.

Contents
Chinese Abstract i
English Abstract iii
Acknowledgements v
Contents vi
Figure Captions ix
Table Captions xv
Chapter 1 Introduction 1
Chapter 2 Band-to-Band Tunneling Hot Hole Stress Induced Leakage Current (SILC) in Tunnel Oxides
2.1 Introduction 11
2.2 Hot Hole SILC Characterization 12
2.3 Hot Hole SILC Mechanism 18
2.4 Results and Discussions 22
2.4.1 Tunnel Detrapping Properties of Ib 23
2.4.2 Recombination of Trapped Holes 27
2.4.3 Surface Generation Leakage 27
2.5 Summary 30
Chapter 3 Role of Positive Oxide Charges in SILC by Anode Hot Hole Stress
3.1 Introduction 32
3.2 Mechanisms for FN SILC 34
3.3 Characteristics of FN SILC 36
3.3.1 SILC Transients in a -FN Stressed Device 38
3.3.2 The DC component of +FN SILC 40
3.4 Positive Oxide Charge Annealing Effect 45
3.5 Summary 47
Chapter 4 Significance of Positive Charge Assisted Tunneling to Flash EEPROM Device Reliability
4.1 Introduction 50
4.2 Numerical Simulation of HH SILC 50
4.3 Results and Discussions 54
4.3.1 Time- and Field-dependence 54
4.3.2 Erase Biases Dependence 60
4.3.3 Oxide Thickness Dependence 64
4.3.4 Structure and Process Dependence 69
4.4 Summary 73
Chapter 5 Constraint of the Charge Pumping Method in Ultra-thin Gate Oxide MOSFETs
5.1 Introduction 77
5.2 The Characteristics of Charge Pumping Current in Ultra-thin Oxide 78
5.3 Biasing Window for Charge Pumping Method 84
5.4 Summary 88
Chapter 6 The Origin of Substrate Current in Post Soft Breakdown nMOSFETs
6.1 Introduction 89
6.2 Experimental Setup 90
6.3 Mechanisms for Substrate Current 94
6.4 Results and Discussions 94
6.4.1 Electrical Properties 94
6.4.2 Hot Carrier Luminescence 99
6.4.3 The Detection of SBD Position 103
6.5 Summary 103
Chapter 7 Conclusions 107
Reference 109
Vita 121
Publication Lists 122

Reference
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Chapter 2
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Chapter 3
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[3.10] Q. Lu, K. P. Cheung, N. A. Ciampa, C. T. Liu, C-P. Chang, J. I. Colonell, W-Y-C. Lai, R. Liu, J. F. Miner, H. Vaidya, C-S. Pai and J. T. Clemens, “A Model of the Stress Time Dependence of SILC,” Int. Rel. Physics Symp., pp396-399,1999
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[3.12] B. Doyle, M. Bourcerie, J. C. Marchetaux and A. Boudou, “Interface Trap Creation and Charge Trapping in the Medium-to-High Gate Voltage Range (Vd/2VgVd) during Hot-Carrier Stressing of n-MOS Transistors,” IEEE Trans. Electron Devices, Vol. 37, pp. 744-754, 1990
Chapter 4
[4.1] Z. A. Weinberg, "Tunneling of Electrons from Si into Thermally Grown SiO2," Solid-State Electronics, Vol. 20, pp. 11-18, 1977
[4.2] I. Lundsorm and C. Svensson, "Tunneling to Traps in Insulator," J. Appl. Phys., Vol. 43, pp. 5045-5047, 1972
[4.3] A. Meinertzhagen, C. Petit, M. Joudain, F. Mondon, "Stress Induced Leakage Current Reduction by a Low Field of Opposite Polarity to the Stress Field," J. Appl. Phys., Vol. 84, pp. 5070-5079, 1998
[4.4] S. Manzini and A. Modelli, "Tunneling Discharge of Trapped Holes in Silicon Dioxide," in Insulating Films on Semiconductors edited by J. F. Verweij and Wolters, Elsevier Science Publishers, North Holland, pp. 112-115, 1983
[4.5] M. Kato, N. Miyamoto, H. Kume, A. Satoh, M. Ushiyama and K. Kimura, “Read-Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash Memories,” IEDM Tech. Dig., pp. 45-48, 1994
[4.6] B. Doyle, M. Bourcerie, J. C. Marchetaux and A. Boudou, “Interface Trap Creation and Charge Trapping in the Medium-to-High Gate Voltage Range (Vd/2 ≦ Vg ≦ Vd) during hot-carrier stressing of n-MOS transistors,” IEEE Trans. Electron Device, Vol. 37, pp. 744-754, 1990
[4.7] C. Huang, T. Wang, T. Chen, N. C. Peng, A. Chang and F. C. Shone, "Characterization and Simulation of Hot Carrier Effect on Erasing Gate Current in Flash EEPROMs," Proc. Int. Reliability Phys. Symp., pp. 61-64, 1995
[4.8] K. Kobayashi, A. Teramoto and M. Hirayama, “Model for the Substrate Hole Current Based on Thermionic Hole Emission from the Anode during Fowler-Nordheim Electron Tunneling in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors,” J. Appl. Phys., Vol. 77, p. 3277, 1995
[4.9] Y. Nissan-Cohen, J. Shappir and D. Frohman-Bentchkowsky, “High Field and Current Induced Positive Charge in Thermal SiO2 Layers,” J. Appl. Phys., Vol. 57, pp. 2830-2839, 1985
[4.10] I. C. Chen, S. Holland, K. K. Young, C. Chang and C. Hu, "Substrate Hole Current and Oxide Breakdown," Appl. Phys. Lett., Vol. 49, pp. 669-671, 1986
[4.11] D. J. DiMaria, “Hole Trapping, Substrate Currents, and Breakdown in Thin Silicon Dioxide Films,” IEEE Elect. Dev. Lett., Vol. 16, pp. 184-186, 1995
[4.12] S. Takagi, N. Yasuda and A. Toriumi, “Experimental evidence of inelastic tunneling and new I-V model for stress-induced leakage current,” IEDM Tech. Dig., pp. 323-326, 1996
[4.13] S. Takagi, N. Yasuda, and A. Toriumi, “Experimental Evidence of In-elastic Tunneling in Stress-Induced Leakage Current,” IEEE Trans. Electron Devices, vol. 46, pp. 335—341, Feb. 1999
[4.14] E. Rosenbaum and L. F. Register, “Mechanism of Stress-Induced Leakage Current in MOS Capacitors,” IEEE Trans. Elect. Dev., Vol. 44, pp. 317-323, 1997
[4.15] T. Ogata, M. Inoue, T. Nakamura, N. Tsuji, K. Kobayashi, K. Kawase, H. Kurokawa, T. Kaneoka, Y. Ohno and H. Miyoshi, ”Impact of Nitridation Engineering on Microscopic SILC Characteristics of Sub-10-nm Tunnel Dielectrics,” IEDM, pp. 597-600, 1998
Chapter 5
[5.1] B.E. Weir, P.J. Silverman, D. Monroe, K.S. Krisch, M.A. Alam, G.B. Alers, T.W. Sorsch, G.L. Timp, F. Baumann, C.T. Liu, Y. Ma and D. Hwang, “Ultra-thin Gate Dielectrics: They Breakdown Down, But Do They Fail?,” IEDM Tech. Dig., pp. 73-76, 1997
[5.2] P. Masson, J. L. Autran and J. Brini, " On the Tunneling Component of Charge Pumping Current in Ultrathin Gate Oxide MOSFET's," IEEE Elect. Dev. Lett., Vol. 20, pp. 92-94, Feb., 1999
[5.3] S. S. Chung, S. J. Chen, C. K. Yang, S. M. Cheng, S. H. Lin, Y. C. Sheng, H. S. Lin, K. T. Hung, D. Y. Wu, T. R. Yew, S. C. Chien, F. T. Liou and F. Wen, “A Novel and Direct Determination of the Interface Traps in Sub-100nm CMOS Devices with Direct Tunneling Regime (12-16A) Gate Oxide,” in Symp. on VLSI Tech. Dig., pp. 74-75, 2002
[5.4] A. Ghetti, E. Sangiorgi, J. Bude, T. W. Sorsch, and G. Weber, “ Low Voltage Tunneling in Ultra-Thin Oxide: a Monitor for Interface states and Degradation,” IEDM Tech. Dig., pp. 731-734, 1999
[5.5] G. Groeseneken, Herman E. Maes, N. Beltran and Roger F. De Keersmaecker, “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors,” IEEE Trans. Elect. Dev., Vol. 31, pp. 42-53, Jan, 1984
[5.6] Y. Shi, T. P. Ma, S. Prasad and S. Dhanda, " Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFETs," IEEE Trans. Elect. Dev., Vol. 45, pp. 2355-2360, Nov., 1998
[5.7] T. H. Ning,"Electron Trapping in SiO2 due to Electron-Beam Deposition of Aluminum," Appl. Phys.,Vol. 47(7), pp4077-4082,1978
Chapter 6
[6.1] M. Depas, T. Nigam, and M. Heyns, “Soft breakdown of ultra-thin gate oxide layers,” IEEE Trans. Electron Devices, vol. 43, p. 1499, Sept., 1996.
[6.2] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, and H. E. Maes, “Characteristics and Correlated Fluctuations of the Gate and Substrate Current after Oxide Soft-Breakdown,” Solid State Devices and Materials, Hiroshima, 1998, pp. 144-145
[6.3] B.E. Weir, P.J. Silverman, D. Monroe, K.S. Krisch, M.A. Alam, G.B. Alers, T.W. Sorsch, G.L. Timp, F. Baumann, C.T. Liu, Y. Ma and D. Hwang, “Ultra-thin Gate Dielectrics: They Breakdown Down, But Do They Fail?,” IEDM Tech. Dig., pp. 73-76, 1997
[6.4] M. Rasras, I. D. Wolf, G. Groeseneken, R. Degraeve, and H. E. Maes, "Substrate Hole Current Origin after Oxide Breakdown," IEDM Tech. Dig., pp.537-540, 2000
[6.5] F. Crupi, G. Iannaccone, I. Crupi, R. Degraeve, G. Groeseneken and H. E. Maes, “Characterization of Soft Breakdown in Thin Oxide NMOSFETs Based on the Analysis of the Substrate Current,” IEEE Trans. Electron Devices, vol. 48, June, p. 1109, 2001
[6.6] N. Yang, W. K. Henson, and J. J. Wortman, “ Analysis of Tunneling Currents and Reliability of NMOSFET with Sub-2nm Gate Oxides,” IEDM Tech. Dig., pp. 453-456, 1999
[6.7] A. Ghetti, E. Sangiorgi, J. Bude, T. W. Sorsch, and G. Weber, “ Low Voltage Tunneling in Ultra-Thin Oxide: a Monitor for Interface states and Degradation,” IEDM Tech. Dig., pp. 731-734, 1999
[6.8] Y. Shi, T.P.Ma, S. Prasad, and S. Dhanda, “Polarity Dependent Gate Tunneling Currents in Dual-Gate CMOSFET,” IEEE Trans. on Elect. Dev., vol. 45, no. 11, November, pp.2355-2360, 1998
[6.9] S. H. Lee, B. J. Cho, J. C. Kim and S. H. Choi, “Quasi-breakdown of Ultra-thin Gate Oxide under High Field Stress,” IEDM Tech. Dig., pp. 605-608, 1994
[6.10] B. Kaczer, R. Degraeve, A. De Keersgieter, Koen Van de Mieroop, V. Simons and G. Groeseneken, “Consistent Model for Short-Channel nMOSFET After Hard Gate Oxide Breakdown,” IEEE Trans. on Elect. Dev., Vol. 49, March, pp. 507-513, 2002
[6.11] B. Kaczer, R. Degraeve, A. De Keersgieter, M. Rasras, G. Groeseneken, “Explanation of nMOSFET Substrate Current after Hard Gate Oxide Breakdown,” Microelectronic Engineering, Vol. 59, pp. 155-160, 2001
[6.12] J. D. Bude, B. E. Weir and P. J. Silverman, “ Explanation of Stress-Induced Damage in Thin Oxides,” IEDM Tech. Dig., pp. 179-182, 1998
[6.13] A. Ghetti, M. A. Alam, J. Bude, D. Monroe, E. Sangiorgi, and H. Vaidya,” Analysis of Trap-Assisted Conduction Mechanisms through Silicon Dioxide Films Using Quantum Yield,” IEDM Tech. Dig., pp. 723-726, 1999
[6.14] B.P. Linder, J.H. Stathis, R.A. Wachnik, E. Wu, S.A. Cohen, A. Ray and A. Vayshenker, “Gate Oxide Breakdown under Current Limited Constant Voltage Stress,” in Symp. VLSI., pp. 214-215, 2000
[6.15] M. Lanzoni, E. Sangiorgi, C. Fiegna, M. Manfredi and B. Ricco, “Extended (1.1-2.9eV) hot-carrier induced photon emission in n-channel Si MOSFET’s,” IEEE Electron Device Lett., Vol. 12, pp. 341-343, 1991
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