臺灣博碩士論文加值系統

傳統低溫複晶矽薄膜電晶體使用電漿輔助化學氣相沉積系統(PECVD)沉積之TEOS oxide或Si3N4為其閘極介電層，此種低溫介電層含有非常多的缺陷與極低之崩潰電壓，常常造成低溫複晶矽薄膜電晶體的電特性與可靠度不佳。因此，製作低溫高品質的閘極介電層，以提升低溫複晶矽薄膜電晶體製程的電特性是迫切需要的技術。本論文中，我們提出具備新穎ONO堆疊式閘極介電層結構之低溫複晶矽薄膜電晶體，以ONO堆疊式閘極介電層系統分三段製程步驟連續成長此ONO (TEOS Oxide/Si3N4/N2O-plasma Oxide)堆疊式介電層結構。首先，以PECVD N2O電漿成長約30Å之高品質超薄氧化層，再接著堆疊400Å之Si3N4，最後再沉積70Å之TEOS氧化層，完成此新穎ONO (TEOS Oxide/Si3N4/N2O-plasma Oxide) 堆疊式閘極介電層之製作。由電性研究顯示，使用此ONO堆疊式閘極介電層的低溫複晶矽薄膜電晶體比傳統TEOS氧化層低溫複晶矽薄膜電晶體具有更佳的元件電特性及可靠度，以及較低的複晶矽通道缺陷密度，此乃因N2O電漿成長的高品質超薄氧化層與複晶矽形成平坦並有極強Si≡N鍵結的界面，並且成長過程中的N2O電漿鈍化機制 (passivation) 引致大量的氮原子與氧原子修補複晶矽的缺陷所造成的改善。此外，ONO介電層結構中的Si3N4層具有比SiO2高之介電常數，則進一步的提升低溫複晶矽薄膜電晶體之驅動電流，然而PECVD Si3N4可能含有大量的缺陷，且Si3N4易與上層複晶矽閘極的形成不佳的界面，所以我們的ONO結構中設計沉積上層的薄TEOS氧化層，以改善與多晶矽閘極的界面缺陷。
另外，我們利用氨氣 (NH3) 電漿處理，進一步填補降低複晶矽薄膜電晶體的通道缺陷。我們發現氨氣電漿處理可以大幅的改善薄膜電晶體的電特性，尤其對載子移動率 (carrier mobility)、開關電流比 (On/Off current ratio) 及元件可靠度方面的改善效果卓越，這歸功於矽原子與氨氣中的氮/氫原子形成鍵結(Si-N/Si-H)，而填補在通道中grain boundaries和複晶矽薄膜與閘極介電層介面間的dangling bond。
為了更進一步提升元件的電特性，我們將新型ONO堆疊式閘極介電層運用於凹陷式通道 (Recessed-Channel) 結構的薄膜電晶體中，源極和汲極的厚度較通道墊高500Å 之poly-Si薄膜，讓通道的厚度較薄而形成凹陷處。這樣設計的好處是，在凹陷通道區上，當使用準份子雷射結晶技術時，可橫向成長出較大的晶粒，使得載子移動率大幅增加，進而提升元件的驅動電流能力。此外，由於源極和汲極位於較厚的區域，可降低串聯電阻，使得元件特性得到進一步的改善。

Traditionally, low temperature polycrystalline silicon thin-film transistors (LTPS TFTs) were fabricated with PECVD TEOS oxide or Si3N4 as gate insulator. However, the poly-Si TFT with such low quality dielectric films shows poor electric characteristics and reliability due to a large amount of defects and traps in the PECVD TEOS oxide or Si3N4 films. Therefore, a new low temperature process of making high-quality gate dielectric film is necessary for fabricating high performance low-temperature poly-Si TFTs. In this thesis, low-temperature poly-Si TFTs with a novel ONO stack dielectric structure (TEOS Oxide/Si3N4/N2O-plasma oxide) in-situ grown by plasma-enhanced chemical vapor deposition (PECVD) system were presented. The ONO stack gate dielectric structure is composed of bottom layer N2O-plasma grown 30Å ultrathin oxide, middle layer 400Å nitride film and top layer 70Å TEOS oxide. It is found that low-temperature poly-Si TFTs with a novel ONO stack dielectric structure have superior electrical properties, more remarkable reliability and lower interface trap density than traditional TEOS oxide ones. These improvements were attributed to the high quality N2O-plasma grown ultrathin oxide forming smoother surface and strong Si≡N bonds at the oxide/polysilicon interface. In the other hands, N2O plasma passivation effect induces large amount of nitrogen and oxygen atoms passivated the traps in the polysilicon grain boundaries. Furthermore, the middle layer nitride film which has higher dielectric constant than silicon dioxide results in promoting the driving current of poly-Si TFTs. However, the nitride/poly-Si gate interface was not so good as respected and thick nitride film maybe includes a large amount of defects. So we deposited a thin 70Å-thick TEOS oxide as upper layer in our novel ONO structure to improve the interface between gate dielectric and poly-Si gate.
In the other way, we further utilized ammonia (NH3) plasma passivation method to promote electrical characteristics of poly-Si TFTs. NH3-plasma passivation can improve enormously the poly-Si TFTs performances, particularly in carrier mobility, on/off current ratio, and reliability. The improvement can be attributed to the nitrogen pile-up at gate dielectric/poly-Si interface and the strong Si-N/Si-H bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films.
In order to further promote the device electrical characteristics, we used the ONO stack gate dielectric on new recessed-channel structure TFTs (RC-TFTs). This recessed-channel structure was formed by the thick source/drain regions and the thin channel region. The advantage of RC-TFTs structure is the lag of solidification in thin regions generates lateral thermal gradients and urging grains to grow longitudinally from the thick S/D regions to the thin channel region along the channel when using excimer laser crystallization to recrystallize the ploy-Si films. This kind of grain configuration improves the field effect mobility and results in promoting the device driving current. In addition, since the thickness of source/drain regions can be made thicker, the series resistance of these devices will not increase significantly, and device performance can be further improved.

Contents
Chinese Abstract i
English Abstract iii
Acknowledgment v
Contents vi
Table Captions viii
Figure Captions ix
Chapter 1 Introduction
1.1 Overview of Polycrystalline Silicon Thin-Film Transistors Technology 1
1.2 Poly-Si Recrystallization Methods 2
1.2.1 Solid-phase crystallization method 2
1.2.2 Excimer laser annealing crystallization method 3
1.2.3 Metal-induce lateral rystallization method 3
1.2.4 Rapid thermal annealing crystallization method 4
1.3 Low-Temperature Plasma Grown Gate Dielectric Technology 4
1.4 Motivation 5
1.5 Thesis Outline 6
1.6 References 6
Chapter 2 Experimental of Low-Temperature Poly-Si TFTs with
a Novel ONO Stack Gate Dielectric
2.1 The Fabrication Process Flow of Low-Temperature Poly-Si TFTs 10
2.2 Methods of Device Parameter Extraction 12
2.2.1 Determination of threshold voltage (Vth) 12
2.2.2 Determination of subthreshold swing 13
2.2.3 Determination of field effect mobility (μFE) 13
2.2.4 Determination of on/off current ratio 14
2.2.5 Extraction of grain boundary trap state density (Nt) 14
2.3 References 16
Chapter 3 The Characteristics of Low-Temperature Poly-Si
TFTs with a Novel ONO Stack Gate Dielectric
3.1 The Electrical Properties of ONO Stack Gate Dielectric 17
3.2 The Characteristics of Low-Temperature Poly-Si TFTs with ONO stack gate dielectric 19
3.3 The Characteristics of Low-Temperature Poly-Si TFTs with different interfacial layer within ONO gate dielectric 21
3.4 Improving the Characteristics of Low-Temperature Poly-Si TFTs by NH3 Plasma Passivation 23
3.4 Summary 23
3.4 References 24
Chapter 4 High Performance Recessed-Channel TFTs (RC-TFTs) with a Novel ONO Stack Gate Dielectric
4.1 Introduction of Recessed-Channel TFTs (RC-TFTs) 26
4.2 The Fabrication process flow of Recessed-Channel TFTs with a Novel ONO Stack Gate Dielectric 26
4.3 The Characteristics of Recessed-Channel TFTs with a Novel ONO Stack Gate Dielectric 27
4.4 References 28
Chapter 5 Conclusions and Future Works
5.1 Conclusions 29
5.2 Future Works 30

chapter 1
[1] T. Serilawa, S.shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility Poly-Si TFTs for large-area LCD’s”, IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1929,1989.
[2] S. Ikeda et al., “Apolysilicon transistor technology for large capacity SRAMs”, IEDM Tech. Dig., pp.469, 1990.
[3] F. Hayashi and M. Kitakata, “A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond,” VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on , 1992 , p36 —37
[4] S. Morozumi et al., “Completely integrated contact-type linear image sensor”, IEEE Trans. Electron Dev., vol. 21, no. 8, p. 1546, 1985.
[5] Y. Hayashi et al., “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chip”, ESSCC Digest, pp. 266, 1988.
[6] F. Okumura et al., in IDRC Digest, p. 174, 1988.
[7] N. Yamauchi, Y. Inaba, and M. Okamura, “An integrated photodetector amplifer using α-Si p-i-n photodiodes and poly-Si thin-film transistos,” IEEE Photonic Tec. Lett., vol. 5, no. 3, p.319, 1993.
[8] H. C. Lin et al., “Deposition and Device application of in situ Boron doped Polycrystalline SiGe Films Grown at Low Temperature”, J. Appl Phys. Lett., vol. 42, no. 9, pp. 835-837, 1993
[9] H. C. Tuan, “Amorphous silicon thin film and its applications to large-area elements”, Mater. Rec. Soc. Ump. Proc., vol. 33, p247, 1984.
[10] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si”, IEEE proc. Circuits Devices Syst., vol. 131, no. 1, p.38, 1994.
[11] M. G. Clark, “Current status and future prospects of Poly-Si devices,” IEEE Proc.-Circuits Devices Syst., Vol. 141, No. 1, February 1994.
[12] A. Nakamura, F. Emoto, E. Fujii, and A. Tamamoto “A High-Reliablity, Low-Operation-voltage Monolithic Active-Matrix LCD by Using Advanced Solid-Phase growth Technique,” IEDM Tech. P.847, 1990.
[13] N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method.” IEEE Trans. Electron Devices, vol. 40, pp. 1876-1879, Oct. 1994.
[14] G. K. Giust and T. W. Sigmon, “Low-Temperature Polysilicon Thin-Film Transistors Fabricated from Laser-Processed Sputtered-Silicon Films,” IEEE Electron Device Lett., vol. 19, pp. 343-344, Sept. 1998.
[15] G. K. Giust and T. W. Sigmon, “High-Performance Laser-Processed Polysilicon Thin-Film Tranasitor,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77-79, Feb. 1999.
[16] Zhiguo Meng, Mingxiang Wang, and Man Wong, Member, IEEE, “High Performance Low Temperature Mateal-Induced Unilaterally Crystallized polycrystalline Silicon Thin Film transistors for System-on-Panel Applications,” IEEE Trans. Electron Devices, vol.47, no.2, Feb. 2000.
[17] Seok-Woon Lee, Tae-Hyung Ihn, and Seung-Ki Joo, “Fabrication of High-Mobility P-Channel Poly-Si Thin Film Transistos by Self-Aligned Metal-Induced Lateral Crystallization,” IEEE Electron Device Lett., vol. 17, no.8 Aug. 1996.
[18] Won Kyu Kwak, Bong Rae Cho, Soo Young Yoon, Seong Jin Park, And Jin Jang, “A High Performace Thin-Film Transistor Using a Low Temperature Poly-Si by Silicide Mediated Crystallization,” IEEE Electron Device Lett., vol. 21, no.3 March 2000.
[19] Eric Campo, Emmanuel Scheid, Danielle Bielle-Daspet, and Jean-Paul Guillemet, “Influence of Rapid Thermal and Low Temperature Processing on the Electrical Properties of Polysilicon Thin Film Transistos,” IEEE Trans. on Semi. Manufacturing, vol. 8, no.3 Aug. 1995.
[20] Yong Woo Choi, Jeong o Lee, Tae Woong Jang, and Byung Tae Ahn, “Thin-Film Transistors Fabricated with Poly-Si Films Crystallized at Low Temperature by Microwave Annealing,” IEEE Electron Device Lett., vol. 20, no. 1, pp. 2-4, Jan. 1999.
[21] I. W. Wu, T. Y. Huang, W. B. Jackson, A.G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, no.4, p.181, 1991.
[22] T. I. Kamins, and P. J. Marcoux, “Hydrogenation of transistors fabricated in polycrystalline-silicon films,” IEEE Electron Device Lett., vol. 1, no. 8, p.159, 1980.
[23] R. A. Ditizio, S. J. Fonash, and B. C. Hseih, “Examination of the optimization of thin film transistor passivation with hydrogen electron cyclotron resonance plasma,” J. Vac. Sci. Technol. A, vo. 10, no. 1, p 59, 1992.
[24] M. Hack, A. G. Lewis, and I. W. Wu, “physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, no. 5, p. 890, 1993.
[25] K. Nakazawa, “Recrystallization of amorphous silicon films deposited by low-pressure chemical vapor deposition from Si2H6 gas,” J. Appl. Phys., vol. 60, pp.1703-1706, 1991.
[26] J. W. Lee, N. I. Lee, S. H. Hur, and C. H. Han, “Oxidation of silicon using electron cyclotron resonance nitrous oxide plasma and its application to polycrystalline silicon thin film transistors,” J. Electrochem. Soc. Vol. 133, pp.3238, 1997.
[27] C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chjen, S. K. Hsien, and T. Y. Huang, “Plasma-induced charging damage in ultrathin (3nm) nitrided oxides,” IEEE Electron Device Letters, vol. 21, p. 15-17, Jan. 2000
chapter 2
[1] T. Serilawa, S.shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility Poly-Si TFTs for large-area LCD’s”, IEEE Trans. Electron Dev., vol. 36, no. 9, pp. 1929,1989.
[2] S. Ikeda et al., “Apolysilicon transistor technology for large capacity SRAMs”, IEDM Tech. Dig., pp.469, 1990.
[3] F. Hayashi and M. Kitakata, “A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond,” VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on , 1992 , p36 —37
[4] S. Morozumi et al., “Completely integrated contact-type linear image sensor”, IEEE Trans. Electron Dev., vol. 21, no. 8, p. 1546, 1985.
[5] Y. Hayashi et al., “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chip”, ESSCC Digest, pp. 266, 1988.
[6] F. Okumura et al., in IDRC Digest, p. 174, 1988.
[7] N. Yamauchi, Y. Inaba, and M. Okamura, “An integrated photodetector amplifer using α-Si p-i-n photodiodes and poly-Si thin-film transistos,” IEEE Photonic Tec. Lett., vol. 5, no. 3, p.319, 1993.
[8] H. C. Lin et al., “Deposition and Device application of in situ Boron doped Polycrystalline SiGe Films Grown at Low Temperature”, J. Appl Phys. Lett., vol. 42, no. 9, pp. 835-837, 1993
[9] H. C. Tuan, “Amorphous silicon thin film and its applications to large-area elements”, Mater. Rec. Soc. Ump. Proc., vol. 33, p247, 1984.
[10] J. R. Ayres and N. D. Young, “Hot carrier effects in devices and circuits formed from poly-Si”, IEEE proc. Circuits Devices Syst., vol. 131, no. 1, p.38, 1994.
[11] M. G. Clark, “Current status and future prospects of Poly-Si devices,” IEEE Proc.-Circuits Devices Syst., Vol. 141, No. 1, February 1994.
[12] A. Nakamura, F. Emoto, E. Fujii, and A. Tamamoto “A High-Reliablity, Low-Operation-voltage Monolithic Active-Matrix LCD by Using Advanced Solid-Phase growth Technique,” IEDM Tech. P.847, 1990.
[13] N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method.” IEEE Trans. Electron Devices, vol. 40, pp. 1876-1879, Oct. 1994.
[14] G. K. Giust and T. W. Sigmon, “Low-Temperature Polysilicon Thin-Film Transistors Fabricated from Laser-Processed Sputtered-Silicon Films,” IEEE Electron Device Lett., vol. 19, pp. 343-344, Sept. 1998.
[15] G. K. Giust and T. W. Sigmon, “High-Performance Laser-Processed Polysilicon Thin-Film Tranasitor,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77-79, Feb. 1999.
[16] Zhiguo Meng, Mingxiang Wang, and Man Wong, Member, IEEE, “High Performance Low Temperature Mateal-Induced Unilaterally Crystallized polycrystalline Silicon Thin Film transistors for System-on-Panel Applications,” IEEE Trans. Electron Devices, vol.47, no.2, Feb. 2000.
[17] Seok-Woon Lee, Tae-Hyung Ihn, and Seung-Ki Joo, “Fabrication of High-Mobility P-Channel Poly-Si Thin Film Transistos by Self-Aligned Metal-Induced Lateral Crystallization,” IEEE Electron Device Lett., vol. 17, no.8 Aug. 1996.
[18] Won Kyu Kwak, Bong Rae Cho, Soo Young Yoon, Seong Jin Park, And Jin Jang, “A High Performace Thin-Film Transistor Using a Low Temperature Poly-Si by Silicide Mediated Crystallization,” IEEE Electron Device Lett., vol. 21, no.3 March 2000.
[19] Eric Campo, Emmanuel Scheid, Danielle Bielle-Daspet, and Jean-Paul Guillemet, “Influence of Rapid Thermal and Low Temperature Processing on the Electrical Properties of Polysilicon Thin Film Transistos,” IEEE Trans. on Semi. Manufacturing, vol. 8, no.3 Aug. 1995.
[20] Yong Woo Choi, Jeong o Lee, Tae Woong Jang, and Byung Tae Ahn, “Thin-Film Transistors Fabricated with Poly-Si Films Crystallized at Low Temperature by Microwave Annealing,” IEEE Electron Device Lett., vol. 20, no. 1, pp. 2-4, Jan. 1999.
[21] I. W. Wu, T. Y. Huang, W. B. Jackson, A.G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, no.4, p.181, 1991.
[22] T. I. Kamins, and P. J. Marcoux, “Hydrogenation of transistors fabricated in polycrystalline-silicon films,” IEEE Electron Device Lett., vol. 1, no. 8, p.159, 1980.
[23] R. A. Ditizio, S. J. Fonash, and B. C. Hseih, “Examination of the optimization of thin film transistor passivation with hydrogen electron cyclotron resonance plasma,” J. Vac. Sci. Technol. A, vo. 10, no. 1, p 59, 1992.
[24] M. Hack, A. G. Lewis, and I. W. Wu, “physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, no. 5, p. 890, 1993.
[25] K. Nakazawa, “Recrystallization of amorphous silicon films deposited by low-pressure chemical vapor deposition from Si2H6 gas,” J. Appl. Phys., vol. 60, pp.1703-1706, 1991.
[26] J. W. Lee, N. I. Lee, S. H. Hur, and C. H. Han, “Oxidation of silicon using electron cyclotron resonance nitrous oxide plasma and its application to polycrystalline silicon thin film transistors,” J. Electrochem. Soc. Vol. 133, pp.3238, 1997.
C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chjen, S. K. Hsien, and T. Y. Huang, “Plasma-induced charging damage in ultrathin (3nm) nitrided oxides,” IEEE Electron Device Letters, vol. 21, p. 15-17, Jan. 2000
chapter 3
Byung-Hyuk Min, Cheol-Min Park, and Min-Koo Han “ Electrical Characteristics of Poly-Si TFT’s with Smooth Surface Roughness at Oxide/Poly-Si Interface” IEEE Trans. Electron Devices, vol. 44, pp. 2036—2038, 1997.
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chapter 4
C. W. Lin, L. J. Cheng, Y. L. Lu, Y. S Lee, and H. C. Chung “High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure,” IEEE Electron Device Lett., vol. 22, no. 6, June. 2001.
[2] M. Chan, F. Assaderaghi, S. A. Parke, C. Hu, and P. K. Ko, “Recessed-channel structure for fabricating ultra-thin SOI MOSFET with low series resistance,” IEEE Electron Device Lett., vol. 15, pp. 22—24, Jan. 1994.
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[4] M. Hack, I-W. Wu, T. J. King and A. G.. Lewis, “Analysis of leakage currents in poly-silicon thin-film transistors,” Electron Devices Meeting, 1993. Technical Digest., International, p. 385, 1993.