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[1] Ali Hajimiri et al., “A General Theory of Phase Noise in Electrical Oscillators,” IEEE JSSC, Vol. 33, pp. 179, 1998 [2] S. Christensson et al. “Low Frequency Noise in MOS Transistors-I,” IEEE Solid-State Electronics, Vol. 11, pp. 797, 1968 [3] Ewout P. Vandamme et al. “Critical Discussion on Unified 1/f Noise Models for MOSFETs,” IEEE TED, Vol. 47, pp. 2146, 2000 [4] L. K. J. Vandamme et al. “Noise as a Diagnostic Tool for Quality and Reliability of Electronic Devices,” IEEE TED, Vol. 41, pp. 2176, 1994 [5] Aldert Van Der Ziel “Unified Presentation of 1/f Noise in Electronic Devices: Fundamental 1/f Noise Sources,” Proceeding of the IEEE, Vol. 76, pp. 233, 1988 [6] Kwok K. Hung et al., “A Unified Model for the Flicker Noise in Metal-Oxide-Semiconductor Field-Effect Transistors,” IEEE TED, Vol. 37, pp. 654, 1990 [7] Kwok K. Hung et al. “A Physics-Bases MOSFET Noise Model for Circuit Simulators,” IEEE TED, Vol. 37, pp. 1323, 1990 [8] F. N. Hooge “1/f Noise Sources,” IEEE TED, Vol. 41, pp. 1926, 1994 [9] Ray Jayaraman et al., “A 1/f Noise Technique to Extract the Oxide Trap Density near the Conduction Band Edge of Silicon,” IEEE TED, Vol. 36, pp. 1773, 1989 [10] K. K. Hung et al. “Flicker Noise Characteristic of Advanced MOS Technologies,” IEEE IEDM, pp.34, 1988 [11] Aldert Van Der Ziel “Noise in Solid State Devices and Circuits,” John Wiley & Sons, 1986 [12] Paul R. Gray et al. “Analysis and Design of Analog Integrated Circuits,” John Wiley & Sons, 2001 [13] Shinji Odanaka et al. “Double Pocket Architecture Using Indium and Boron for Sub-100 nm MOSFETs,” IEEE EDL, Vol. 22, pp. 330, 2001 [14] Hyunsang Hwang et al. “Degradation of MOSFETs Drive Current Due to Halo Ion Implantation,” IEEE IEDM, pp. 21.4.1, 1996 [15] Romain Gwoziecki et al. “Optimization of Vth Roll-Off in MOSFET’s with Advanced Channel Architecture─Retrograde Doping and Pockets,” IEEE TED, Vol. 46, pp. 1551, 1999 [16] Bin Yu et al. “Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submicronmeter MOSFET’s,” IEEE TED, Vol. 44, pp. 627, 1997 [17] Hemant V. Deshpande et al. “Analog Device Design for Low Power Mixed Mode Application in Deep Submicron CMOS Technology,” IEEE EDL, Vol. 22, pp. 588, 2001 [18] T. Ohguro et al, “0.12mm Raised Gate/Source/Drain Epitaxial Channel NMOS Technology,” IEEE IEDM, pp. 34.4.1, 1998 [19] T. Ohguro et al. “An Epitaxial Channel MOSFET for Improving Flicker Noise under Low Supply Voltage,” IEEE Symposium on VLSI, pp. 160, 2000 [20] Robert G.H. Lee et al. “A new Method for Characterizing the Spatial Distributions of Interface States and Oxide-Trapped Charges in LDD n-MOSFET’s,” IEEE TED, Vol. 43, pp. 81, 1996 [21] Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE TED, Vol. 45, pp.512, 1998 [22] Ming-Horn Tsai et al, “The Impact of Device Scaling on the Current Fluctuation in MOSFET’s,” IEEE TED, Vol. 41, pp. 2061, 1994 [23] Rafael Rios et al. “A Three-Transistor Threshold Voltage Model for Halo Process,” IEEE IEDM, 2002 [24] Scott Martin et al. “BSIM3 Based RTS and 1/f Noise Models Suitable for Circuit Simulators,” IEEE IEDM, pp.85, 1998 [25] Hans van Meer, “Limitation of Shift-and-Ratio Based Leff Extraction Techniques for MOS Transistors with Halo or Pocket Implants,” IEEE EDL, Vol. 21, pp.133, 2000 [26] Yuan Taur et al. “A New “Shift and Ratio” Method for MOSFET Channel-Length Extraction,” IEEE EDL, Vol.13, pp.267, 1992 [27] Yuan Taur, “MOSFET Channel Length: Extraction and Interpretation,” IEEE TED, Vol. 47, pp. 160, 2000 [28] Fariborz Assaderaghi et al. “A Dynamic Threshold Voltage MOSFET (DTMOSFET) for Ultra-Low Voltage Operation,” IEEE IEDM, pp. 809, 1994 [29] M. Jamal Deen et al. “Effect of Forward and Reverse Substrate Biasing on Low-Frequency Noise in Silicon PMOSFETs,” IEEE TED, Vol. 49, pp. 409, 2002 [30] Tsun-Lai Hsu et al. “Low-Frequency Noise Properties of Dynamic Threshold (DT) MOSFET’s,” IEEE EDL, Vol. 20, pp.532, 1999 [31] Fariborz Assaderaghi et al. “Dynamic Threhold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEEE TED, Vol. 44, pp. 414, 1997 [32] Hioraki Ueno et al. “Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFET for Circuit Simulation,” IEEE TED, Vol. 49, pp. 1783, 2002 [33] Luca Larcher et al. “Impact of Programming Charge Distribution on Threshold Voltage and Subthreshold Slope of NROM Memory Cells,” IEEE TED, Vol. 49, pp.1939, 2002 [34] E. Lusky et al. “Characterization of Channel-hot-electron Injection by the Subthreshold Slope of NROM Device,” IEEE EDL, Vol. 22, pp.556, 2001
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