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研究生:陳巨峰
研究生(外文):Chu-Feng Chen
論文名稱:以快速升溫氧化技術成長1.0nm高品質氮氧化矽閘極絕緣層及其特性研究
論文名稱(外文):The investigation of 1.0 nm high-quality oxynitride gate dielectric was grown by rapid thermal process
指導教授:張國明桂正楣
指導教授(外文):Kow-Ming ChangCheng-May Kwei
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:42
中文關鍵詞:氮氧化矽快速升溫氧化技術
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當互補式金氧半場效電晶體的閘極通道長度微縮到100奈米以下時,閘極介電層的有效電性厚度將縮小至1.5奈米以下,但是達此超薄厚度之二氧化矽絕緣膜其直接穿遂電流將大到無可忍受的程度,為有效降低閘極介電層的漏電電流,在本文中我們利用快速升溫製程技術(RTP)來成長高品質的超薄氮氧化矽 (Oxynitride) 閘極絕緣層,藉由控制成長時間、成長溫度與氮氣/氧氣的混和比例成長,可獲得超低漏電流之1.0 奈米超薄氮氧化矽 (Oxynitride) 絕緣層。吾人實驗結果顯示最佳之RTP氧化製程條件為N2/O2混合比例為5/1 (10 slm/2 slm),於900℃成長15 sec。此最佳條件成長之氮氧化矽絕緣膜,其物理厚度可達到1.0奈米,有效電性厚度可以達到0.86奈米 (EOT = 0.86 nm),而且其閘極漏電流密度比純氧氣成長的二氧化矽氧化層小100倍。1.0奈米氮氧化矽絕緣膜有超低漏電電流的原因是,於適當的氮氣與氧氣混合比例的氧化環境下,有大量的氮原子累積於矽基材與氧化層介面,並形成較強的矽氮鍵結,進而增加介電層的抗壓特性與減少界面缺陷,大幅的改善超薄氧化層的特性。

When the gate oxide thickness downs to 1.0 nm regime, the direct-tunneling current becomes main key issue for high-performance CMOS beyond 0.1μm. In my research work, we have developed high-quality silicon oxynitride (SiON) with physical thickness 1.0 nm (EOT = 0.86 nm) gate dielectric using rapid thermal processing (RTP). The 1.0 nm ultra-thin oxynitride was grown by rapid thermal process in N2 and O2 mixed gas ambient, in term of oxidation temperature, process time control and the flow ratio of N2/O2 mixed gas as comparison with O2 grown oxide. The thickness of oxynitride film is determined by ellipsometer and verified by high resolution TEM (HR-TEM). The experiments show that 1.0nm SiON oxynitride grown by RTP at 900℃ for 15 sec has the lowest density of the interface states and the leakage current is two orders lower than that of a RTO sample. This excellent experimental result is due to a proper amount of nitrogen incorporated in the thin oxynitride film during RTP oxidation process in N2/O2 mixed gas ambient. The nitrogen incorporated can improve the integrity of thin oxynitride film and the interface state between the Si-substrate and ultra-thin oxynitride film.

Contents
Chinese Abstract i
English Abstract ii
Acknowledgment iii
Contents iv
Table Captions vi
Figure Captions vii
Chapter 1 Introduction
1.1 Overview of Ultra Thin Oxide Technology 1
1.2 Which one is the next generation gate dielectric candidate? 2
1.3 Rapid thermal processing (RTP) 4
1.4 Motivation 5
1.5 Thesis Outline 6
1.6 References 7
Chapter 2 Fabrication of ultra-thin 1.0 nm-thick oxynitride
2.1 The fabrication of capacitor with 1.0 nm oxynitride film 11
2.2 Devices measurement method 13
2.2.1 Determination of gate dielectric thickness 13
2.2.2 C-V and J-V measurement 14
2.3 References 14
Chapter 3 Physical Properties and Electrical Characteristics of 1.0 nm Ultra-thin Oxynitride Films
3.1 The effect of N2/O2 gas flow ratios on thickness of ultra-thin oxynitride films 17
3.2 The electrical characteristics of 1.0 nm ultra-thin oxynitride films 18
3.2.1 The effect of N2/O2 gas flow ratios on gate leakage current 19
3.2.2 The C-V characteristicis of 1.0 nm ultra-thin oxynitride films 19
3.3 Reducing leakage current by RTP post annaling 20
3.3.1 The post annealing effect on gate leakage current 21
3.2.2 The C-V characteristicis of 1.0 nm ultra-thin oxynitride films with post annaling 22
3.4 Summary 22
3.5 References 23
Chapter 4 Conclusions and Future Works
4.1 Conclusions 25
4.2 Future Work 26

[1] Iwai, H.; Momose, H.S. “Ultra-thin gate oxides-performance and reliability” IEDM '98 Technical Digest., International , 6-9 Dec 1998 ,pp.163 -166
[2] Timp, G.; Agarwal, A.; Bourdella, K.K.; “Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs.” IEDM '98 Technical Digest., International , 6-9 Dec 1998 ,pp. 1041 -1043
[3] Jia Lin; Chai Shumin; Xu Qiuxia; Qian He” Study on ultra-thin gate dielectrics: surface preparation and reliability”, Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on , 1998 ,pp.120 -122
[4] Lai, P.T.; Xu, J.P.; Cheng, Y.C.;” A comparison between NO-annealed O2- and N2O-grown gate dielectrics”, Electron Devices Meeting, 1998. Proceedings., 1998 IEEE Hong Kong , 29 Aug 1998 ,pp.36 -39
[5] Yo-Sheng Lin; Huan-Tsung Huang” On the SiO2-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology”, IEEE Transactions on Electron Devices , vol. 49 Issue: 3 , Mar 2002,
pp.442 -448
[6] Hisayo Sasaki Momose, Shin-ichi Nakamura, Tatsuya Ohguro, “Study of the Manufacturing Feasibility of 1.5-nm Direct-Tunneling Gate Oxide MOSFET’s: Uniformity, Reliability, and Dopant Penetration of the Gate Oxide.”IEEE Transaction on Electron Device, vol. 45, NO. 3, MARCH 1998, pp691-699.
[7] Albert Chin,“Thin Oxides with in situ Native Oxide Removal”, IEEE Electron Device Letters, vol. 18, NO. 9, September 1997, pp417-419.
[8] Albert Chin, ”The Effect of Native Oxide on Thin Gate Oxide Integrity”, IEEE Electron Device Letters, vol. 19, NO. 11, November 1998, pp426-428.
[9] Sorsch, T.; Timp, W.; Baumann, F.H.;” Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology.”, VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on , 9-11 Jun 1998 ,pp. 222 -223
[10] Teong-San Yeoh; Shze-Jer Hu;” Influence of MOS transistor gate oxide breakdown on circuit performance”, Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on , 1998 , pp.59 -63
[11] Satoshi Inaba, Kimitoshi Okano, Satoshi Matsuda,”High Performance 35 nm Gate Length CMOS With NO Oxynitride Gate Dielectric and Ni Salicide” IEEE Transaction on Electron Dvice, vol. 49, NO. 12, December 2002, pp.2263-2270
[12] Technology and Manufacturing Group, Intel Corporation,” Transistor Elements for 30nm Physical Gate Lengths and Beyond”, Intel Technology Journal, vol. 06 Issue 02 Published, May 16, 2002
[13] Takayanagi-Takagi, M.; Toyoshima, Y.; “Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs” IEDM '98 Technical Digest., International , 6-9 Dec 1998 pp.575 -578
[14] Satoshi Inaba, Kimitoshi Okano, Satoshi Matsuda,” High Performance 35 nm Gate Length CMOS WithNO Oxynitride Gate Dielectric and Ni Salicide” IEEE Transaction on Electron Devices, vol. 49, NO. 12, December 2002, pp.2263-2269
[15] Xin Guo, T. P. Ma,” Tunneling Leakage Current in Oxynitride: Dependence on Oxygen/Nitrogen Content” IEEE Electron Device Letters, vol. 19, NO. 6, June 1998, pp.207-209
[16] P. T. Lai, J. P. Xu, and Y. C. Cheng,,” Interface Properties of NO-Annealed N O-Grown Oxynitride”, IEEE Transaction on Electron Device, vol. 46, NO. 12, December 1999, pp.2311-2314
[17] Tung Ming Pan, Tan Fu Lei,”Robust Ultrathin Oxynitride Dielectrics by NH3 Nitridation and N2O RTA Treatment”, IEEE electron device letter, vol. 21, NO. 8, August 2000, pp.378-380
[18] Tung Ming Pan, Tan Fu Lei, ”Characterization of Ultrathin Oxynitride (18—21 Å) Gate Dielectrics by NH3 Nitridation and N2O RTA Treatment.” IEEE Transaction on Electron devices , vol. 48, NO. 5, May 2001,pp.907-912
[19] W. H. Lin, K. L. Pey, Z. Dong ,”Effects of Post-Deposition Anneal on the Electrical Properties of Si3N4 Gate Dielectric”, IEEE electron device letters, vol. 23, NO. 3, March 2002, pp.124-126
[20] C. G. Parker, G. Lucovsky, and J. R. Hauser,” Ultrathin Oxide—Nitride Gate Dielectric MOSFET’s”, IEEE electron device letters, vol. 19, NO. 4, April 1998, pp.106-108
[21] Chein-Hao Chen, Yean-Kuen Fang, Chih-Wei Yang,” To Optimize Electrical Properties of the Ultrathin (1.6 nm) Nitride/Oxide Gate Stacks With Bottom Oxide Materials and Post-Deposition Treatment”, IEEE Transaction on Electron Devices, vol. 48, NO. 12, December 2001, pp.2769-2776
[22] De Keyser, R.; Donald, J., III;” Model based predictive control in RTP semiconductor manufacturing”, Control Applications, 1999. Proceedings of the 1999 IEEE International Conference on , vol. 2 , 1999 pp. 1636 -1641 vol. 2
[23] Liu, C.W.; Lee, M.H.; Chao, C.Y.;”The design of rapid thermal process for large diameter applications”, Semiconductor Manufacturing Technology Workshop, 1998 , 16-17 Jun 1998 ,pp. 61 -70
[24] Chin-Yang Chen, Ming-Jer Jeng, and Jenn-Gwo Hwu ,”Rapid Thermal Post oxidation Anneal Engineering in Thin Gate Oxides with Al Gates”, IEEE Transaction on Electron Devices, vol. 45, NO. 1, January 1998, pp 247-253
[25] Peters, S.; Lee, J.Y.; Ballif, C.;” Rapid thermal processing: a comprehensive classification of silicon materials”, Photovoltaic Specialists Conference, 2002. Conference Record of the Twenty-Ninth IEEE , 2002 ,pp. 214 -217
[26] Qiang Lu, Yee Chia Yeo, Kevin J. Yang,” Two Silicon Nitride Technologies for Post-SiO2 MOSFET Gate Dielectric”, IEEE Electron Device Letters, vol. 22, NO. 7, July 2001, pp.324-326
[27] T. P. Ma, Fellow, IEEE,” Making Silicon Nitride Film a Viable Gate Dielectric”, IEEE Transaction on Electron Devices , vol. 45, NO. 3, MARCH 1998, pp.680-690
[28] Ying Shi; Xiewen Wang; Tso-Ping Ma,” Electrical properties of high-quality ultrathin nitride/oxide stack dielectrics”, IEEE Transactions on Electron Devices, vol. 46 Issue: 2 , Feb 1999 , pp.362 -368
[29] Chien-Hao Chen, Yean-Kuen Fang,,” Downscaling Limit of Equivalent Oxide Thickness in Formation of Ultrathin Gate Dielectric by Thermal-Enhanced Remote Plasma Nitridation” IEEE Transaction on Electron Devices, vol. 49, NO. 5, May 2002, pp.840-846
[30] C. H. Chen, Y. K. Fang, C. W. Yang,” Thermally-Enhanced Remote Plasma Nitrided Ultrathin (1.65 nm) Gate Oxide with Excellent Performances in Reduction of Leakage Current and Boron Diffusion”, IEEE Electron Device Letters, vol. 22, NO. 8, August 2001, pp.378-380
[1] Online: http://www.thermawave.com.Therma-Wave, Inc., Fremont, CA
[2] Online: http://www.tencor.comKLA-Tensor, Inc, San Jose, CA
[3] D.E. Aspnes, J. B. Theeten, and F. Hottier, “Investigation of effective-medium models of microscopic surface roughness by spectroscopic ellipsometry,” Phys. Rev. B, vol. 20, p.3513, 1977
[4] B. Fowler and E. O’Brien, “Relationships between the material properties of silicon oxide films deposited by electron cyclotron resonance chemical vapor deposition and their use as an indicator of the dielectric constant,” J. Vac. Sci. Technol. B: Microeletron. Nanometer Struct., vol. 12, pp. 441-448, January 1994
[5] G. Lucovsky, M. J Mantini, J. K. Srivastava, and E. A. Irene, “Low-temperature growth of silsicon dioxide films: A study of chemical bonding by ellipsometer and infrared spectroscopy,” J. Vac. Sci. Technol. B: Microeletron. Nanometer Struct., vol. 5, no.2, pp. 530-537, March 1987
[6] Khaled Ahmed, Effiong Ibok, “Comparative physical and electrical metrology of ultra-thin oxide in the 6 to 1.5 nm regime,” IEEE Transactions on Electron Devices, vol. 47, no. 7, July 2000
[7] H.S. Momose, M.One, T. Yoshitomi, “Quantum-mechanical modeling of accumulation layers in MOS structure,” IEEE Trans. Electron Devices, vol.39, pp.1732-1739, July 1992
[8] K.Yang, Y.-C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in VLSI Technology Symp. Tech. Dig., Kyoto, Japan, 1999, pp. 77-78.
[9] W. K.Henson, K.Z.Ahmed, “Estimating oxide thickness of tunnel oxide down to 1.4 nm using conventional C-V measurements on MOS capacitors,” IEEE Electron Device Lett., vol.20, pp.179-181, Apr, 1999
[10] R.Rios and N.D. Arora, “Determination of ultra-thin gate oxide thickness for CMOS structures using quantum effects,” in IEDM Tech. Dig., 1994, pp. 613-616.
[11] C. H. Chen, Y. K. Fang, “Determination of deep ultra-thin equivalent oxide thickness (EOT) from measuring flat band C-V curve,” IEEE Transactions on Electron Devices, vol. 49, no.4, April, 2002
[12] Kevin J. Yang and Chenming Hu, “MOS capacitance measurements for high-leakage thin dielectric,” IEEE Transactions on Electron Devices, vol. 46, no.7, July, 1999
[13] Akiko Nara, Naoki Yasuda, “Applicability limits of the two-frequency capaciyance measurement technique for the thickness extraction of ultra-thin gate oxide,” IEEE Transactions on Electron Devices, vol. 15, no.2, May, 2002
[1] W. Ting, H. Hwang, J. Lee, and D.L. Kwong, Appl. Phys. Lett. 57,p.2808, 1990
[2] H.S MOmose, M. One, “1.5nm direct-tunneling gate oxide Si MOSFET’s” IEEE Transactions on, Volume: 43, p.1233 -1234,1996
[3] T. Ohguro, M. Saito, E. Morifuji, “High efficiency 2 GHz power Si-MOSFET design under low supplyvoltage down to 1 V,” in IEDM Tech. Dig., 1996, pp. 83—86.
[4] J. C. Lou, C. Galewski, and W. G. Oldham, “Dichlorosilane effects on low temperature selective silicon epitaxy,” Appl. Phys. Lett., vol. 58, no. 1, pp. 59—61, 1991.
[5] J. Hauser, “Extraction of experimental mobility data for MOS devices,” IEEE Trans. Electron Devices, vol. 43, pp. 1981—1988, Nov. 1996.
[6] S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1497—1508, Aug. 1980.
[7] H. Shin, G. M. Yeric, A. F. Tasch, and C. M. Maziar, “Physically based models for effective mobility and local-field mobility of electrons in MOS inversion layers,” Solid-State Electron., vol. 34, no. 6, pp. 545—552, 1991.
[8] Lo, S.-H.; Buchanan, D.A.; Taur, Y.; Wang, W.; “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's”, IEEE Electron Device Letters, Volume: 18 Issue: 5 , May 1997, p. 209 -211
[9] Xin Guo; Ma, T.P.; “Tunneling leakage curre nt in oxynitride: dependence on oxygen/nitrogen content”, IEEE Electron Device Letters , Volume: 19 Issue: 6 , Jun 1998 ,p.207 —209
[10] D.M. Brown, P.V Gary, “Properties of SixOyNz films on Si”, J. Electronchem. Soc., Vol.115, N o.3, p.311, Mar, 1968
[11] L. He, T. Inokuma, and S. Hasegawa, “Properties of ‘Stoichiometric’ silicon oxynitride films”, Jpn .J. Appl. Phys.,vol. 35, pt 1, no.2B, p.1503, Feb. 1996
[12] V. A. Gritsenko, N. D. Dikovskaja, “Band diagram and conductivity of silicon oxynitride films.” Thin Solid Films, vol. 51, p.353, Feb. 1978
[13] Nara, A.; Yasuda, N.; Satake, H.; Toriumi, A.; “Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultra-thin gate oxide”, Semiconductor Manufacturing, IEEE Transactions on, Volume: 15 ,Issue: 2 , May 2002 ,p. 209 -213
[14] R. R. Razouk and B. E. Deal, “Dependence of interface state density on silicon thermal oxidation process variables.” , J. Electrochem. Soc. Vol. 126 p.1575, 1979
[15] B. E. Deal, M. Sklar, A.S. Grove, and E. H. Snow, “Characterization of the surface state charge of thermally oxidized silicon”, J.Electrochem. Soc. Col. 114, p.226,1967
[16] Chin-Yang Chen; Ming-Jer Jeng; Jenn-Gwo Hwu; “Rapid thermal postoxidation anneal engineering in thin gate oxides with Al gates”, IEEE Transactions on Electron Devices, Volume: 45 Issue: 1 , Jan 1998 ,p.247 —253
[17] R. R. Rasouk and B. E.Deal, “Dependence of interface state density on sislicon thermal oxidation process variables,” J. Electrochem. Soc. Vol.123, p.1575, 1979.
[18] B.E. Deal, M. Sklar, A. S. Grove, and E.H. Snow, “Characterization f the surface atate charge of thermally oxidized silicon,” J. Electrochem. Soc. Vol.114, p.226, 1967.
[19] S.S. Cohen, “Electrical properties of post anneal thin SiO2 films”, J. Electrochem. Soc. Vol.130,p.929,1983
[20] S. Holland and C. Hu, “Correlation between breakdown and process induced positive charge trapping in thin film”, J. Electrochem. Soc. Vol. 133 p.1705, 1986
[21] J. M. Aitken and D. R. Young, “Avalanche injection of hole into SiO2”, IEEE Trans. Nucl. Sci, Vol. NS-24, p.2128,1977
[22] P. Balk, M. Aslam, and D. R. Young, “High temperature annealing behavior of electron traps in thermal SiO2”, Solid-State Electron. Vol.27, p.2151, 1975
[23] Wright, P.J.; Kermani, A.; Saraswat, K.C.; “Nitridation and post-nitridation anneals of SiO2 for ultrathin dielectrics “, IEEE Transactions on Electron Devices, Volume: 37, Issue: 8, Aug 1990 ,p.1836 —1841
[24] S. Iaba, T. Shimizu, “Dvice performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics.”, IEDM, p651-654, 2002

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