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研究生:陳巨峰
研究生(外文):Chu-Feng Chen
論文名稱:以快速升溫氧化技術成長1.0nm高品質氮氧化矽閘極絕緣層及其特性研究
論文名稱(外文):The investigation of 1.0 nm high-quality oxynitride gate dielectric was grown by rapid thermal process
指導教授:張國明桂正楣
指導教授(外文):Kow-Ming ChangCheng-May Kwei
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:42
中文關鍵詞:氮氧化矽快速升溫氧化技術
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當互補式金氧半場效電晶體的閘極通道長度微縮到100奈米以下時,閘極介電層的有效電性厚度將縮小至1.5奈米以下,但是達此超薄厚度之二氧化矽絕緣膜其直接穿遂電流將大到無可忍受的程度,為有效降低閘極介電層的漏電電流,在本文中我們利用快速升溫製程技術(RTP)來成長高品質的超薄氮氧化矽 (Oxynitride) 閘極絕緣層,藉由控制成長時間、成長溫度與氮氣/氧氣的混和比例成長,可獲得超低漏電流之1.0 奈米超薄氮氧化矽 (Oxynitride) 絕緣層。吾人實驗結果顯示最佳之RTP氧化製程條件為N2/O2混合比例為5/1 (10 slm/2 slm),於900℃成長15 sec。此最佳條件成長之氮氧化矽絕緣膜,其物理厚度可達到1.0奈米,有效電性厚度可以達到0.86奈米 (EOT = 0.86 nm),而且其閘極漏電流密度比純氧氣成長的二氧化矽氧化層小100倍。1.0奈米氮氧化矽絕緣膜有超低漏電電流的原因是,於適當的氮氣與氧氣混合比例的氧化環境下,有大量的氮原子累積於矽基材與氧化層介面,並形成較強的矽氮鍵結,進而增加介電層的抗壓特性與減少界面缺陷,大幅的改善超薄氧化層的特性。

When the gate oxide thickness downs to 1.0 nm regime, the direct-tunneling current becomes main key issue for high-performance CMOS beyond 0.1μm. In my research work, we have developed high-quality silicon oxynitride (SiON) with physical thickness 1.0 nm (EOT = 0.86 nm) gate dielectric using rapid thermal processing (RTP). The 1.0 nm ultra-thin oxynitride was grown by rapid thermal process in N2 and O2 mixed gas ambient, in term of oxidation temperature, process time control and the flow ratio of N2/O2 mixed gas as comparison with O2 grown oxide. The thickness of oxynitride film is determined by ellipsometer and verified by high resolution TEM (HR-TEM). The experiments show that 1.0nm SiON oxynitride grown by RTP at 900℃ for 15 sec has the lowest density of the interface states and the leakage current is two orders lower than that of a RTO sample. This excellent experimental result is due to a proper amount of nitrogen incorporated in the thin oxynitride film during RTP oxidation process in N2/O2 mixed gas ambient. The nitrogen incorporated can improve the integrity of thin oxynitride film and the interface state between the Si-substrate and ultra-thin oxynitride film.

Contents
Chinese Abstract i
English Abstract ii
Acknowledgment iii
Contents iv
Table Captions vi
Figure Captions vii
Chapter 1 Introduction
1.1 Overview of Ultra Thin Oxide Technology 1
1.2 Which one is the next generation gate dielectric candidate? 2
1.3 Rapid thermal processing (RTP) 4
1.4 Motivation 5
1.5 Thesis Outline 6
1.6 References 7
Chapter 2 Fabrication of ultra-thin 1.0 nm-thick oxynitride
2.1 The fabrication of capacitor with 1.0 nm oxynitride film 11
2.2 Devices measurement method 13
2.2.1 Determination of gate dielectric thickness 13
2.2.2 C-V and J-V measurement 14
2.3 References 14
Chapter 3 Physical Properties and Electrical Characteristics of 1.0 nm Ultra-thin Oxynitride Films
3.1 The effect of N2/O2 gas flow ratios on thickness of ultra-thin oxynitride films 17
3.2 The electrical characteristics of 1.0 nm ultra-thin oxynitride films 18
3.2.1 The effect of N2/O2 gas flow ratios on gate leakage current 19
3.2.2 The C-V characteristicis of 1.0 nm ultra-thin oxynitride films 19
3.3 Reducing leakage current by RTP post annaling 20
3.3.1 The post annealing effect on gate leakage current 21
3.2.2 The C-V characteristicis of 1.0 nm ultra-thin oxynitride films with post annaling 22
3.4 Summary 22
3.5 References 23
Chapter 4 Conclusions and Future Works
4.1 Conclusions 25
4.2 Future Work 26

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