臺灣博碩士論文加值系統

本篇論文主旨在設計一個具有線性補償電路之功率放大器，其規格設定為Bluetooth。所下三顆分別為: 用來比較用之傳統功率放大器、具有PMOS補償電路及共模消除電路之功率放大器及具有gm3線性補償電路之功率放大器。這三個晶片皆是使用標準點25微米1P5M 互補式金氧半導體製程，其中，具有gm3線性補償電路之功率放大器正在製作中。量測結果顯示，傳統功率放大器的晶片可以在2.7GHz的頻率下提供20.39 dBm的輸出功率，同時有著24%的效率;使用2.5V電源的情況下，功率放大器晶片之工作電流為156mA， 在輸出等於20dBm下，兩訊號(two-tones) IM3 量測值約為-16.26dBc，550kHz頻寬下ACPR值為21dB。由量測的結果可驗証，這個功率放大器的規格適合工作在短距離無線傳輸的應用上，而且可以符合Bluetooth class 1的輸出功率規格(20dBm)及線性度要求規格。但具有PMOS補償電路及共模消除電路之功率放大器由於打線電感(bondwires)效應變動影響，量測結果顯示出振盪現象產生，雖仍可量到輸出訊號及功率增益，對線性度而言，頻譜已經很髒無法量測，故無法測量出線性度特性。
由Post-Simulation可知，此兩種具有線性補償之功率放大器，在輸出訊號功率皆等於20dBm時，可以減少1~3dB的三階相互調變訊號(third-order intermodulation distortion, IM3) ，在有共模訊號(common-mode signal)存在的情況下，由於此兩電路可提供較高的共模抑制比(Common-mode rejection ratio, CMRR), 故可降低約3dB IM3值。

This thesis is proposed for designing a CMOS power amplifier with linear compensation. All designs are targeted on the standard of Bluetooth v1.0b. Three power amplifiers are conventional power amplifier, power amplifier with PMOS compensation and common-mode cancellation, and improved gm3 power amplifier. Two of these power amplifiers are designed, proposed, and measured. The improved gm3 power amplifier is in process. All are fabricated in a standard 0.25μm single-poly-five-metal CMOS process. The conventional power amplifier chip can provide 20.39dBm output power with 24% drain efficiency at 2.7GHz. The operating dc current of conventional one is 156mA from 2.5V power supply. At output power equal 20dBm, the IM3 under two-tone test is about -16.26dBc. The ACPR is about 21dB at 550kHz bandwidth. Through measured results, the performance of the proposed CMOS RF power amplifier has been verified to be well suitable for short-range communication applications and can meet Bluetooth output power level class 1(20dBm) and linearity specifications. Unfortunately, the chip with PMOS compensation and common-mode cancellation has oscillation phenomena since the design consideration non-proper. Although it still can measure out the output power and power gain, but the results are not correct enough.
From post-simulation results it can be found that these two types of power amplifier with linear compensation circuit would decrease 1~3dB output third-order intermodulation distortion at output power level equal 20dBm. When a common-mode signal exists, these two types of PA can increase 3dB IM3 values because of high CMRR value.

Chapter 1 Introduction
1.1 Background
1.2 Motivation
1.3 Thesis Organization
Chapter 2 Power Amplifier Background
2.1 Power Amplifier Classes
2.1.1 Class A, AB, B, and C Power amplifiers
2.1.1.1 Class A
2.1.1.2 Class B
2.1.1.3 Class AB
2.1.1.4 Class C
2.1.2 Class D, E, and F Power amplifiers
2.1.2.1 Class D
2.1.2.2 Class E
2.1.2.3 Class F
2.2 Linearization Methods
2.2.1 Feedforward
2.2.2 Feedback
2.2.3 Predistortion
Chapter 3 The Design of a 2.4GHz CMOS Power Amplifier with Linear Compensation
3.1 Design Consideration
3.2 Circuit Design
3.2.1 Output Stage
3.2.2 Pre-Amplification Stage
3.2.3 Common-mode Feedback Circuit
3.2.4 Linearized circuit
3.2.4.1 PMOS cancellation methodology
3.2.4.2 gm3 cancellation methodology
3.3 Simulation Results
3.3.1 Conventional PA
3.3.2. Modified PA
3.3.3 Improved gm3 PA
3.3.4 Comparison of the PA with linearization method and conventional PA
Chapter 4 Experimental Results
4.1 PA Layout Descriptions
4.2 Measurement Setup
4.3 Experimental Results
Chapter 5 Conclusions and Future works
5.1 Conclusions
5.2 Future Works
References

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