(3.227.235.183) 您好!臺灣時間:2021/04/17 11:36
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:華重憲
研究生(外文):Hua,Chung-Hsien
論文名稱:適於數位訊號處理器之低功率多存取埠多存取埠設計
論文名稱(外文):Low Power Multi-Port Register File Design for Digital Signal Processor
指導教授:黃威黃威引用關係
指導教授(外文):Wei Hwang
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:110
中文關鍵詞:低功率多存取埠多存取埠
外文關鍵詞:Low PowerRegister FileMultiple Access
相關次數:
  • 被引用被引用:0
  • 點閱點閱:138
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:12
  • 收藏至我的研究室書目清單書目收藏:1
A low power multiple access port register file suitable for parallel processing processor is proposed in this paper. New register file cell, read/write port architecture and low power circuit design techniques are used in register file design. Static noise margin under the constraint of multiple access ports is discussed and method to maintain static noise margin is proposed. All the results are simulated in TSMC 100nm CMOS technology. A maximum 5X leakage reduction is achieved by using Dual-Vt transistors in the register file cells and 2X energy saving by adjusting the size of the strong inverter compared to normal register file cell design. An optimum sizing ratio is found to trade off between energy consumption and transistor size. Buffer insertion and way to cope with interconnections are also examined in this thesis. Register file architectures for difference types of processors are also proposed and examined in chapter 5. Register file compiler design considerations and testing issues are also address in chapter 5.
A 4W8R 16word 32 bit register file which occupies 1x1 silicon area is implemented. The register file consumes 2mW when 32 bit data are written into the register file in the critical case and clock runs at 2GHz. The load store operation can be completed with one clock cycle. Metal routing and access ports occupy the major part of the overall layout. Low power register file cell and single-ended Read/Write ports are used to reduce power consumption and is especially useful in nano-scale CMOS technology.

A low power multiple access port register file suitable for parallel processing processor is proposed in this paper. New register file cell, read/write port architecture and low power circuit design techniques are used in register file design. Static noise margin under the constraint of multiple access ports is discussed and method to maintain static noise margin is proposed. All the results are simulated in TSMC 100nm CMOS technology. A maximum 5X leakage reduction is achieved by using Dual-Vt transistors in the register file cells and 2X energy saving by adjusting the size of the strong inverter compared to normal register file cell design. An optimum sizing ratio is found to trade off between energy consumption and transistor size. Buffer insertion and way to cope with interconnections are also examined in this thesis. Register file architectures for difference types of processors are also proposed and examined in chapter 5. Register file compiler design considerations and testing issues are also address in chapter 5.
A 4W8R 16word 32 bit register file which occupies 1x1 silicon area is implemented. The register file consumes 2mW when 32 bit data are written into the register file in the critical case and clock runs at 2GHz. The load store operation can be completed with one clock cycle. Metal routing and access ports occupy the major part of the overall layout. Low power register file cell and single-ended Read/Write ports are used to reduce power consumption and is especially useful in nano-scale CMOS technology.

Chapter 1 Introduction
Chapter 2 Low Power Circuit Design Techniques
Chapter 3 Low Power Multi-Port Register File Cell Design
Chapter 4 Low Power Decoder Design
Chapter 5 Register File Organizations in Different Types of Processors
Chapter 6 Conclusion and Future Work

Bibliography
Reference of Chapter 1
[1.1] Minoru Nagata, ‘Limitations, Innovations, and Challenges of Circuits and Devices into a Half Micrometer and Beyond’, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 465-472, April 1992.
[12.] Anathna P Chandrakasan, Samuel Sheng, and Robert W Brodersen, ‘Low-Power CMOS Digital Design’, IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, April 1992.
[1.3] Katsuhiro Shimohigashi and Koichi Seki, ‘Low-Voltage ULSI Design’, IEEE Journal of Solid-State Circuits, vol. SC-28, no. 4, pp. 408-413, April 1993.
[1.4] Richard F Lyon, ‘Cost, Power amd Parallelism in Speech Signal Processing’, IEEE Custom Integrated Circuits Conference, pp. 15.1.1-15.1.9, 1993.
Reference of Chapter 2
[2.1] Fornaciari, W.; Gubian, P.; Sciuto, D.; Silvano, C.,; “High-level power estimation of VLSI systems”, Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International vol.3 Symposium on , Volume: 3 , 9-12 Jun 1997, Page(s): 1804 -1807
[2.2] Nemani, M.; Najm, F.N.,;”High-level area and power estimation for VLSI circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 18 Issue: 6 , Jun 1999 , Page(s): 697 -713
[2.3] Gupta, S.; Najm, F.N.;,”Power modeling for high-level power estimation”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 8 Issue: 1 , Feb 2000, Page(s): 18 -29
[2.4] Duarte, D.; Narayanan, V.; Irwin, M.J.; Kandemir, M.;, ”Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks”, VLSI Design, 2001. Fourteenth International Conference on , 2001, Page(s): 248 -253
[2.5] C.C. Wu, C.H. Diaz, B.L. Lin, S.Z. Chang, C.C. Wang, J.J. Liaw, C.H. Wang, K.K. Young, K.H. Lee, B.K. Liew, J.Y.C Sun. “Ultra-low leakage 0.16 um CMOS for low-standby power applications.” International Electron Devices Meeting (IEDM), 1999. p.671-4.
[2.6] Kuroda, T.; Hamada, M., “Low-power CMOS digital design with dual embedded adaptive power supplies”, Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 4 , Apr 2000, Page(s): 652 -655
[2.7] Y. Kado et al. “Substantial advantages of fully-depleted CMOS/SIMOX devices as low-power high-performance VLSI components compared with its bulk-CMOS counterpart.” International Electron Devices Meeting (IEDM), 1995. p.635-8.
[2.8] K. Fujii, T. Douseki, M. Harada. “A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction.” IEEE International Solid-State Circuits Conference. (ISSCC), 1998. p.190-1.
[2.9] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai. “Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration.” IEEE Custom Integrated Circuits Conference (CICC), 2000. p.409-12.
[2.10] H. Kawaguchi, K Nose, T. Sakurai. “A super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with pico ampere Stand by Current”, IEEE Journal Of Solid State Circuits, Vol. 35,No 10, 2000, p.1498-501.
[2.11] Naffziger, S.D.; Colon-Bonet, G.; Fischer, T.; Riedlinger, R.; Sullivan, T.J.; Grutkowski, T.;, “The implementation of the Itanium 2 microprocessor”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 11 , Nov 2002, Page(s): 1448 -1460
[2.12] Dake Liu; Svensson, C.;, “Power consumption estimation in CMOS VLSI chips”, Solid-State Circuits, IEEE Journal of , Volume: 29 Issue: 6 , Jun 1994, Page(s): 663 -670
[2.13] Benini, L.; De Micheli, G.; Macii, E., “Designing low-power circuits: practical recipes”, IEEE Circuits and Systems Magazine , Volume: 1 Issue: 1 , 2001, Page(s): 6 -25
[2.14] Athas, W., “Low-power VLSI techniques for applications in embedded computing”, Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on , 1999 Page(s): 14 -22
[2.15] Fornaciari, W.; Gubian, P.; Sciuto, D.; Silvano, C., “A conceptual analysis framework for low power design of embedded systems”, Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on , 1996 Page(s): 170 -179
[2.16] Kim, J.; Horowitz, M.A.;, “Adaptive supply serial links with sub-1-V operation and per-pin clock recovery”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 11 , Nov 2002, Page(s): 1403 -1413
[2.17] Jaeha Kim; Horowitz, M.A.;, “An efficient digital sliding controller for adaptive power-supply regulation”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 5 , May 2002, Page(s): 639 -647
[2.18] Gu-Yeon Wei; Kim, J.; Liu, D.; Sidiropoulos, S.; Horowitz, M.A.;, “A variable-frequency parallel I/O interface with adaptive power-supply regulation”, Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 11 , Nov 2000, Page(s): 1600 -1610
[2.19] Kuroda, T.; Hamada, M.;, “Low-power CMOS digital design with dual embedded adaptive power supplies”, Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 4 , Apr 2000, Page(s): 652 -655
[2.20] Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang;, “Dual threshold voltage domino logic synthesis for high performance with noise and power constraint”, Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings , 2002, Page(s): 260 -265
[2.21] Rongtian Zhang; Roy, K., “Low-power high-performance double-gate fully depleted SOI circuit design”, Electron Devices, IEEE Transactions on , Volume: 49 Issue: 5 , May 2002, Page(s): 852 -862
[2.22] Zhang, R.; Roy, K.; Janes, D.B., “Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design”, Low Power Electronics and Design, International Symposium on, 2001. , 2001, Page(s): 213 -218
[2.23] Sandararajan, V.; Parhi, K.K., “Synthesis of low power CMOS VLSI circuits using dual supply voltages”, Design Automation Conference, 1999. Proceedings. 36th , 1999 Page(s): 72 -75
[2.24] Manzak, A.; Chakrabarti, C., “A low power scheduling scheme with resources operating at multiple voltages”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 10 Issue: 1 , Feb. 2002 Page(s): 6 -14
[2.25] Embacher, M.; Hoeld, W.; Mahnke, T.; Stechele, W., “Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis”, Electronics, Circuits and Systems, 2002. 9th International Conference on , Volume: 2 , 2002 Page(s): 697 -700
[2.26] Embacher, M.; Hoeld, W.; Mahnke, T.; Panenkal, S.; Stechele, W., “Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness”, Electronics, Circuits and Systems, 2002. 9th International Conference on , Volume: 2 , 2002 Page(s): 701 -704
[2.27] Sundararajan, V.; Parhi, K.K., “Low power synthesis of dual threshold voltage CMOS VLSI circuits”, Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on , 1999 Page(s): 139 -144
[2.28] Lijun Gao; Parhi, K.K., “Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec”, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on , Volume: 4 , 2001 Page(s): 574 -577 vol. 4
[2.29] Inoue, A.; Dklobdzija, V.G.; Walker, W.W.; Kai, M.; Izawa, T., ”A low power SOI adder using reduced-swing charge recycling circuits”, Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International , 2001 Page(s): 316 -317, 459
[2.30] Prasad, S.C.; Roy, K., “Circuit optimization for minimization of power consumption under delay constraint”, VLSI Design, 1995., Proceedings of the 8th International Conference on , 1995 Page(s): 305 -309
[2.31] Llopis, R.P.; Sachdev, M., “Low power, testable dual edge triggered flip-flops”, Low Power Electronics and Design, 1996., International Symposium on , 1996 Page(s): 341 -345
[2.32] Afghahi, M., “A robust single phase clocking for low power, high-speed VLSI applications”, Solid-State Circuits, IEEE Journal of , Volume: 31 Issue: 2 , Feb. 1996 Page(s): 247 -254
[2.33] Radhakrishnan, D., “ Low-voltage low-power CMOS full adder”, Circuits, Devices and Systems, IEE Proceedings- , Volume: 148 Issue: 1 , Feb 2001 Page(s): 19 -24
[2.34] Parameswar, A.; Hara, H.; Sakurai, T., “A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications”, Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994 , 1994 Page(s): 278 -281
[2.35] Bai-Sun Kong; Joo-Sun Choi; Seog-Jun Lee; Kwyro Lee, “Charge recycling differential logic for low-power application”, Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International , 1996 Page(s): 302 -303, 462
[2.36] Bum-Sik Kim; Dae-Hyun Chung; Lee-Sup Kim, “A new 4-2 adder and booth selector for low power MAC unit”, Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on , 1997 Page(s): 100 -103
[2.37] Anis, M.H.; Allam, M.W.; Elmasry, M.I.;, “Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 10 Issue: 2 , Apr 2002, Page(s): 71 -78
[2.38] Mutoh, S.; Shigematsu, S.; Gotoh, Y.; Konaka, S.;, “Design method of MTCMOS power switch for low-voltage high-speed LSIs”, Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific , 18-21 Jan 1999, Page(s): 113 -116 vol.1
[2.39] Shigematsu, S.; Mutoh, S.; Matsuya, Y.; Tanabe, Y.; Yamada, J.;, “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits”, Solid-State Circuits, IEEE Journal of , Volume: 32 Issue: 6 , Jun 1997, Page(s): 861 -869
[2.40] Kawaguchi, H.; Nose, K.; Sakurai, T.;, “A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current”, Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 10 , Oct 2000, Page(s): 1498 -1501
[2.41] Inukai, T.; Takamiya, M.; Nose, K.; Kawaguchi, H.; Hiramoto, T.; Sakurai, T.;, “Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration”, Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000 , 2000, Page(s): 409 -412
[2.42] Kumagai, K.; Iwaki, H.; Yoshida, H.; Suzuki, H.; Yamada, T.; Kurosawa, S.;, “A novel powering-down scheme for low Vt CMOS circuits”, VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on , 11-13 Jun 1998, Page(s): 44 -45
[2.43] Akamatsu, H.; Iwata, T.; Yamamoto, H.; Hirata, T.; Yamauchi, H.; Kotani, H.; Matsuzawa, A.;, “A low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs”, VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on , 13-15 Jun 1996, Page(s): 14 -15
[2.44] van der Meer, P.R.; van Staveren, A.; van Roermund, A.H.M.;, “Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: smart series switch”, Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on , Volume: 4 , 2000, Page(s): 1 -4 vol.4
[2.45] Stan, M.R.; Burleson, W.P., "Bus-invert coding for low-power I/O", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 3 Issue: 1 , Mar 1995, Page(s): 49 -58
[2.46] Hyunsik Im; Inukai, T.; Gomyo, H.; Hiramoto, T.; Sakurai, T.; “VTCMOS characteristics and its optimum conditions predicted by a compact analytical model”, Low Power Electronics and Design, International Symposium on, 2001. , 2001, Page(s): 123 -128
[2.47] Inukai, T.; Hiramoto, T.; Sakurai, T.;, “Variable threshold voltage CMOS (VTCMOS) in series connected circuits”, Low Power Electronics and Design, International Symposium on, 2001. , 2001, Page(s): 201 -206
[2.48] Suzuki, K.; Mita, S.; Fujita, T.; Yamane, F.; Sano, F.; Chiba, A.; Watanabe, Y.; Matsuda, K.; Maeda, T.; Kuroda, T.;, “A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS”, Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997 , 5-8 May 1997, Page(s): 587 -590
[2.49] Kuroda, T.;, “Low power CMOS digital design for multimedia processors”, VLSI and CAD, 1999. ICVC '99. 6th International Conference on , 1999, Page(s): 359 -367
[2.50] Nishikawa, T.; Takahashi, M.; Hamada, M.; Takayanagi, T.; Arakida, H.; Machida, N.; Yamamoto, H.; Fujiyoshi, T.; Maisumoto, Y.; Yamagishi, O.; Samata, T.; Asano, A.; Terazawa, T.; Ohmori, K.; Shirakura, J.; Watanabe, Y.; Nakamura, H.; Minami, S.; Kuroda, “A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM”, Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International , 2000, Page(s): 230 -231, 460
[2.51] Roy, K.; Krishnammthy, R., “Design of low voltage CMOS circuits”, Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on , 2001, Page(s): 3.2.1 -3.2.29
[2.52] Jaewon Oh; Pedram, M., “Gated clock routing for low-power microprocessor design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 20 Issue: 6 , June 2001, Page(s): 715 -722
[2.53] An-Yeu Wu; Liu, K.J.R., “Algorithm-based low-power transform coding architectures: the multirate approach”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 6 Issue: 4 , Dec. 1998, Page(s): 707 -718
[2.54] Kessels, J., “VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player”, Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on , 1995, Page(s): 44 -52
[2.55] Raghunathan, A.; Jha, N.K., “An ILP formulation for low power based on minimizing switched capacitance during data path allocation”, Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on , Volume: 2, 1995, Page(s): 1069 -1073 vol.2
[2.56] Clark, L.T.; Hoffman, E.J.; Miller, J.; Biyani, M.; Luyun Liao; Strazdus, S.; Morrow, M.; Velarde, K.E.; Yarch, M.A. , ”An embedded 32-b microprocessor core for low-power and high-performance applications “, Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 11 , Nov. 2001, Page(s): 1599 -1608
[2.57] Koegst, M.; Franke, G.; Rulke, S.; Feske, K., “Multi-criterial state assignment for low power FSM design”, Euromicro Conference, 1998. Proceedings. 24th , Volume: 1 , 1998, Page(s): 261 -268 vol.1
[2.58] Guyot, A.; Abou-Samra, S., “Low power CMOS digital design”, Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on , 1998, Page(s): IP6 -I13
[2.59] Kuroda, T. “Low power CMOS digital design for multimedia processors”, VLSI and CAD, 1999. ICVC '99. 6th International Conference on , 1999, Page(s): 359 -367
[2.60] Chandrakasan, A.P.; Sheng, S.; Brodersen, R.W., “Low-power CMOS digital design”, Solid-State Circuits, IEEE Journal of , Volume: 27 Issue: 4 , Apr 1992, Page(s): 473 -484
[2.61] Tzartzanis, N.; Athas, W.C., “Clock-powered logic for a 50 MHz low-power RISC datapath”, Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International, 1997, Page(s): 338 -339, 482
[2.62] Yeh, C.C.; Lou, J.H.; Kuo, J.B., “1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications”, Electronics Letters , Volume: 33 Issue: 16 , 31 July 1997, Page(s): 1375 -1376
[2.63] Yong Moon; Deog-Kyoon Jeong, “An efficient charge recovery logic circuit”, Solid-State Circuits, IEEE Journal of , Volume: 31 Issue: 4 , April 1996, Page(s): 514 -522
[2.64] Zhanping Chen; Johnson, M.; Liqiong Wei; Roy, W.;, “Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacks”, Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on , 10-12 Aug 1998, Page(s): 239 -244
[2.65] Lev, L.A.; Charnas, A.; Tremblay, M.; Dalal, A.R.; Frederick, B.A.; Srivatsa, C.R.; Greenhill, D.; Wendell, D.L.; Duy Dinh Pham; Anderson, E.; Hingarh, H.I.; Razzack, I.; Kaku, J.M.; Shin, K.; Levitt, M.E.; Allen, M.; Ferolito, P.A.; Bartolotti, R.I.; Yu, “A 64-b microprocessor with multimedia support”, Solid-State Circuits, IEEE Journal of , Volume: 30 Issue: 11 , Nov 1995, Page(s): 1227 -1238
[2.66] Wolfe, A.; Fritts, J.; Dutta, S.; Fernandes, E.S.T.; “Datapath design for a VLIW video signal processor”, High-Performance Computer Architecture, 1997., Third International Symposium on , 1-5 Feb 1997, Page(s): 24 -35
[2.67] Tien, C.-K.V.; Lewis, K.; Greub, H.J.; Tsen, T.; McDonald, J.F.; “Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 5 Issue: 2 , Jun 1997, Page(s): 238 -243
[2.68] Miyake, J.; Maeda, T.; Nishimichi, Y.; Katsura, J.; Tainguchi, T.; Yamaguchi, S.; Edamatsu, H.; Watari, S.; Takagi, Y.; Tsuji, K.; Kuninobu, S.; Cox, S.; Duschatko, D.; MacGregor, D.;, “A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store”, Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International , 14-16 Feb 1990, Page(s): 42 -43, 261
[2.69] Vangal, S.; Anders, M.A.; Borkar, N.; Seligman, E.; Govindarajulu, V.; Erraguntla, V.; Wilson, H.; Pangal, A.; Veeramachaneni, V.; Tschanz, J.W.; Ye, Y.; Somasekhar, D.; Bloechel, B.A.; Dermer, G.E.; Krishnamurthy, R.K.; Soumyanath, K.; Mathew, S.; Narend;, “5-GHz 32-bit integer execution core in 130-nm dual-Vt CMOS”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 11 , Nov 2002, Page(s): 1421 -1432
[2.70] Dutta, S.; Wolf, W.; “A circuit-driven design methodology for video signal-processing datapath elements”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 7 Issue: 2 , Jun 1999, Page(s): 229 -240
[2.71] Suzuki, K.; Yamashina, M.; Nakayama, T.; Izumikawa, M.; Nomura, M.; Igura, H.; Heiuchi, H.; Goto, J.; Inoue, T.; Koseki, Y.; Abiko, H.; Okabe, E.; One, A.; Yano, Y.; Yamada, H.; “A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor”, Solid-State Circuits, IEEE Journal of , Volume: 29 Issue: 12 , Dec 1994, Page(s): 1464 -1473
[2.72] Henkels, W.H.; Hwang, W.; Joshi, R.V.;, “ A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch”, VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997, Page(s): 41 -42
[2.73] Asato, C.;, “A 14-port 3.8-ns 116-word 64-b read-renaming register file”, Solid-State Circuits, IEEE Journal of , Volume: 30 Issue: 11 , Nov 1995, Page(s): 1254 -1258
[2.74] Jun-Ho Kwon; Joonho Lim; Soo-Ik Chae;, “A three-port nRERL register file for ultra-low-energy applications”, Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , 2000, Page(s): 161 -166
[2.75] Maly, W.; Patyra, M.; Primatic, A.; Raghavan, V.; Storey, T.; Wolfe, A.; “Memory chip for 24-port global register file”, Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991 , 12-15 May 1991, Page(s): 15.5/1 -15.5/4
[2.76] Takahashi, O.; Silberman, J.; Dhong, S.; Hofstee, P.; Aoki, N.;, “A 690 ps read-access latency register file for a GHz integer microprocessor”, Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings., International Conference on , 5-7 Oct 1998, Page(s): 6 -10
[2.77] Jolly, R.D.;, “A 9-ns, 1.4-gigabyte/s, 17-ported CMOS register file”, Solid-State Circuits, IEEE Journal of , Volume: 26 Issue: 10 , Oct 1991, Page(s): 1407 -1412
[2.78] Golden, M.; Partovi, H.;, “A 500 MHz, write-bypassed, 88-entry, 90-bit register file”, VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on , 1999, Page(s): 105 -108
[2.79] Khellah, M.M.; Elmasry, M.I.;, “Circuit techniques for high-speed and low-power multi-port SRAMs”, ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International , 13-16 Sep 1998, Page(s): 157 -161
[2.80] Franch, R.L.; Ji, J.; Chen, C.L.;, “A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file”, Solid-State Circuits, IEEE Journal of , Volume: 32 Issue: 8 , Aug 1997, Page(s): 1288 -1292
[2.81] Lucas, L.; Greiner, A.;, “Design methodology of a test chip for a portable 8ns 10 ports register file”, Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995 , 1-4 May 1995, Page(s): 29 -32
[2.82] Joshi, R.V.; Hwang, W.; Henkels, W.H.; Wilson, S.; Rausch, W.; Shahidi, G.;, “A 660 MHz self-resetting 8 port, 32×64 bits register file and latch in 0.25 μm SOI technology”, SOI Conference, 1998. Proceedings., 1998 IEEE International , 5-8 Oct 1998, Page(s): 131 -132
[2.83] Joshi, R.V.; Hwang, W.; Wilson, S.C.; Shahidi, G.; Chuang, C.T.;, “Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology”, SOI Conference, 1999. Proceedings. 1999 IEEE International , 1999, Page(s): 79 -81
[2.84] Joshi, R.V.; Hwang, W.; Wilson, S.; Shahidi, G.; Chuang, C.T.;, “Implementation of a high speed multiport register file in a 1.8 V, 0.25 μm CMOS bulk and SOI technology”, VLSI Technology, Systems, and Applications, 1999. International Symposium on , 1999, Page(s): 274 -277
[2.85] Joshi, R.V.; Hwang, W.;, “Design considerations and implementations of a high performance dynamic register file”, VLSI Design, 1999. Proceedings. Twelfth International Conference On , 7-10 Jan 1999, Page(s): 526 -531
[2.86] Wei Hwang; Joshi, R.V.; Henkels, W.H.;, “A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file”, Solid-State Circuits, IEEE Journal of , Volume: 34 Issue: 1 , Jan 1999, Page(s): 56 -67
[2.87] Joshi, R.V.; Hwang, W.; Wilson, S.; Shahidi, G.; Chuang, C.T.;, “A low power 900 MHz register file (8 ports, 32 words×64 bits) in 1.8 V, 0.25 μm SOI technology”, VLSI Design, 2000. Thirteenth International Conference on , 2000, Page(s): 44 -49
[2.88] Joshi, R.V.; Hwang, W.; Wilson, S.C.; Chuang, C.T.;, ““Cool low power” 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology”, Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , 2000, Page(s): 203 -206
[2.89] Khellah, M.M.; Elmasry, M.I.;, “A low-power high-performance current-mode multiport SRAM”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 9 Issue: 5 , Oct 2001, Page(s): 590 -598
[2.90] Tang, S.; Hsu, S.; Ye, Y.; Tschanz, J.; Somasekhar, D.; Narendra, S.; Shih-Lien Lu; Krishnamurthy, R.; De, V.;, “A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques”, VLSI Circuits Digest of Technical Papers, 2002. Symposium on , 2002, Page(s): 320 -321
[2.91] Alvandpour, A.; Krishnamurthy, R.; Soumyanath, K.; Borkar, S.;, “A low-leakage dynamic multi-ported register file in 0.13 μm CMOS”, Low Power Electronics and Design, International Symposium on, 2001. , 2001, Page(s): 68 -71
[2.92] Krishnamurthy, R.K.; Alvandpour, A.; Balamurugan, G.; Shanbhag, N.R.; Soumyanath, K.; Borkar, S.Y.;, “A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 5 , May 2002, Page(s): 624 -632
[2.93] Nomura, M.; Yamashina, M.; Suzuki, K.; Izumikawa, M.; Igura, H.; Abiko, H.; Okabe, K.; Ono, A.; Nakayama, T.; Yamada, H.;, “A 500-MHz, 0.4-μm CMOS, 32-word by 32-bit 3-port register file”, Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995 , 1-4 May 1995, Page(s): 151 -154
[2.94] Tzartzanis, N.; Walker, W.W.; Nguyen, H.; Inoue, A.;, “A 34word x 64b 10R/6W write-through self-timed dual-supply-voltage register file”, Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , Volume: 2 , 2002, Page(s): 338 -537
[2.95] Fetzer, E.S.; Gibson, M.; Klein, A.; Calick, N.; Chengyu Zhu; Busta, E.; Mohammad, B.;, “A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 11 , Nov 2002, Page(s): 1433 -1440
Reference of Chapter 3
[3.1] Seevinck, E.; List, F.J.; Lohstroh, J., “Static-noise margin analysis of MOS SRAM cells”, Solid-State Circuits, IEEE Journal of , Volume: 22 Issue: 5 , Oct 1987, Page(s): 748 -754
[3.2] Bhavnagarwala, A.J.; Xinghai Tang; Meindl, J.D., The impact of intrinsic device fluctuations on CMOS SRAM cell stability, Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 4 , Apr 2001, Page(s): 658 -665
[3.3] Mujtaba, S.A., “Trends in digital signal processors”, VLSI Technology, Systems, and Applications, 1999. International Symposium on , 1999, Page(s): 108 -111
[3.4] Burd, T.D.; Brodersen, R.W., “Design issues for Dynamic Voltage Scaling”, Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , 2000, Page(s): 9 -14
[3.5] Amrutur, B.S.; Horowitz, M.A., “A replica technique for wordline and sense control in low-power SRAM's”, Solid-State Circuits, IEEE Journal of , Volume: 33 Issue: 8 , Aug 1998, Page(s): 1208 -1219
[3.6] Hamzaoglu, F.; Ye, Y.; Keshavarzi, A.; Zhang, K.; Narendra, S.; Borkar, S.; Stan, M.; De, V., “Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation”, Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , 2000, Page(s): 15 -19
[3.7] Powell, M.; Se-Hyun Yang; Falsafi, B.; Roy, K.; Vijaykumar, T.N., “Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories”, Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on , 2000, Page(s): 90 -95
[3.8] Amit Agarwal , Hai Li , Kaushik Roy;, “DRG-cache: a data retention gated-ground cache for low power”, Proceedings of the 39th conference on Design automation June 2002, Page(s): 473 -478
[3.9] Agarwal, A.; Hai Li; Roy, K.; “A single-V/sub t/ low-leakage gated-ground cache for deep submicron”, Solid-State Circuits, IEEE Journal of , Volume: 38 Issue: 2 , Feb 2003, Page(s): 319 -328
Reference of Chapter 4
[4.1] Krishnamurthy, R.K.; Alvandpour, A.; Balamurugan, G.; Shanbhag, N.R.; Soumyanath, K.; Borkar, S.Y., “A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file”, Solid-State Circuits, IEEE Journal of , Volume: 37 Issue: 5 , May 2002, Page(s): 624 -632
[4.2] Amrutur, B.S.; Horowitz, M.A., “Fast low-power decoders for RAMs”, Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 10 , Oct 2001, Page(s): 1506 -1515
[4.3] Zhou, D.; Preparata, F.P.; Kang, S.M.;, “Interconnection delay in very high-speed VLSI”, Circuits and Systems, IEEE Transactions on , Volume: 38 Issue: 7 , Jul 1991, Page(s): 779 -790
[4.4] Ismail, Y.I.; Friedman, E.G.; Neves, J.L., “Repeater insertion in tree structured inductive interconnect”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 48 Issue: 5 , May 2001, Page(s): 471 -481
[4.5] Abou-Seido, A.I.; Nowak, B.; Chu, C., “Fitted Elmore delay: a simple and accurate interconnect delay model”, Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on , 2002, Page(s): 422 -427
[4.6] Gupta, R.; Tutuianu, B.; Pileggi, L.T., “The Elmore delay as a bound for RC trees with generalized input signals”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 16 Issue: 1 , Jan 1997, Page(s): 95 -104
[4.7] Kahng, A.B.; Muddu, S., “An analytical delay model for RLC interconnects”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 16 Issue: 12 , Dec 1997, Page(s): 1507 -1514
Reference of Chapter 5
[5.1] Yen-Kuang Chen; Holliman, M.; Debes, E.; “Video applications on hyper-threading technology”, Multimedia and Expo, 2002. Proceedings. 2002 IEEE International Conference on , Volume: 2 , 2002, Page(s): 193 -196 vol.2
[5.2] Kapasi, U.J.; Dally, W.J.; Rixner, S.; Owens, J.D.; Khailany, B.;, “The Imagine Stream Processor”, Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on , 2002, Page(s): 282 -288
[5.3] Watanabe, K.; Wanming Chu; Yamin Li;, "Exploiting Java instruction/thread level parallelism with horizontal multithreading", Computer Systems Architecture Conference, 2001. ACSAC 2001. Proceedings. 6th Australasian , 2001, Page(s): 122 -129
[5.4] Flynn, M., "Some Computer Organizations and Their Effectiveness", IEEE Trans. Computer, Vol. C-21, pp. 94, 1972.
[5.5] Qing Yang; Tao Yang;, “A memory interference model for regularly patterned multiple stream vector accesses”, Parallel and Distributed Systems, IEEE Transactions on , Volume: 6 Issue: 5 , May 1995, Page(s): 520 -530
[5.6] Corbal, J.; Espasa, R.; Valero, M.;, “DLP+TLP processors for the next generation of media workloads”, High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on , 2001, Page(s): 219 -228
[5.7] Rixner, S.; Dally, W.J.; Khailany, B.; Mattson, P.; Kapasi, U.J.; Owens, J.D.;, “Register organization for media processing”, High-Performance Computer Architecture, 2000. HPCA-6. Proceedings. Sixth International Symposium on , 2000, Page(s): 375 -386
[5.8]Cruz, J.-L.; Gonzalez, A.; Valero, M.; Topham, N.P.;“Multiple-banked register file architectures”, Computer Architecture, 2000. Proceedings of the 27th International Symposium on , 2000, Page(s): 316 -325
[5.9]Zalamea, J.; Llosa, J.; Ayguade, E.; Valero, M.; “Two-level hierarchical register file organization for VLIW processors”, Microarchitecture, 2000. MICRO-33. Proceedings. 33rd Annual IEEE/ACM International Symposium on , 2000, Page(s): 137 -146
[5.10]Balasubramonian, R.; Dwarkadas, S.; Albonesi, D.H.; “Reducing the complexity of the register file in dynamic superscalar processors”, Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on , 2001, Page(s): 237 -248
[5.11] Dutta, S.; Wolf, W.;, “A circuit-driven design methodology for video signal-processing datapath elements”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 7 Issue: 2 , Jun 1999, Page(s): 229 -240
[5.12] Dally, W.J.;, “Interconnect-limited VLSI architecture”, Interconnect Technology, 1999. IEEE International Conference , 1999, Page(s): 15 -17

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔