臺灣博碩士論文加值系統

對於正交分頻多工的通訊系統而言，載波頻率與取樣頻率的同步是非常重要的，影響傳輸效能甚大。而本論文主要的目標就是要尋找一個能夠適用於正交分頻多工無線區域網路的頻率偵測與補償方法。在此我們提出整個偵測與補償組合,其中包括載波飄移頻率取得、殘留載波頻率飄移及取樣頻率飄移的追蹤與補償。對於以封包傳輸的無線區域網路系統，我們在時間區域使用一個二階段載波頻率飄移補償方法。在頻率區域我們將殘留載波頻率飄移及取樣頻率飄移所產生相位旋轉的行為以一線性方程式為模型，產生相位旋轉對次通道的方程式。利用求最接近解的方法取得方程式係數進而加以補償載波頻率與取樣頻率所產生非理想效應。
我們使用IEEE802.11a 標準作為我們模擬環境。 利用Matlab這套軟體建立一完整系統的模擬平台，包括了發射端、傳輸通道模型與接收端。 在傳輸通道模型中，模擬了AWGN、載波頻率飄移、取樣頻率飄移及IEEE多路徑衰減通道。利用我們所提出的方法在IEEE802.11a的標準下可以對抗至少正負100ppm的載波頻率飄移與正負20ppm的取樣頻率飄移。 使IEEE802.11a所提供的各傳輸頻率6Mbps ~ 54Mbps能夠在SNR 2.3dB ~ 20.7dB環境下達到10%的封包錯誤率。最後我們實作了一個包括所提出的載波頻率飄移與取樣頻率飄移補償電路的IEEE802.11a接收端硬體。

The synchronization of carrier frequency and sampling frequency is very important for the OFDM communication system. The target of this study is to find a estimation and compensation method for the OFDM based wireless local area network system. A whole estimation and compensation scheme is proposed including carrier frequency offset acquisition ,remaining carrier frequency offset (CFO) tracking and clock offset compensation. A two stages time domain CFO acquisition scheme is proposed for the packet based OFDM system. The effects of remaining CFO and clock offset are modelled with a linear equation. We find the least square solution and compensate the two effects using the frequency domain phase compensation.
The IEEE802.11a standard is chosen for the simulation environment. We build a complete simulation platform upon the Matlab. It is composed of transmitter, channel and receiver. The channel models the effects of AWGN, CFO, clock offset and IEEE multipath fading channel. We use the proposed method in the IEEE802.11a standard and take care of the interference caused by the CFO and clock offset. The two stages acquisition can make a large CFO estimation range about 100 ppm. And the phase recovery can take care of a 20ppm clock offset. The baseband system achieves 10% PER with SNR of 2.3dB ~ 20.7dB with all data rates of 6Mbits/s ~ 54Mbits/s. The hardware blocks including the CFO acquisition, CFO compensation and phase recovery are proposed and implemented. Finally, the receiver design of our IEEE802.11a is implemented completely and a test chip is tapped out.

1 Introduction 1
1.1 The History of OFDM . . . . . . . . . . . . . . . 1
1.2 OFDM Basic . . . . . . . . . . . . . . . . . . . .2
1.3 Outline . . . . . . . . . . . . . . . . . . . . . 5
2 Synchronization Algorithms 6
2.1 E®ect of Carrier Frequency O®set . . . . . . . . . 6
2.2 Carrier Frequency Offset Synchronization . . . . . 10
2.2.1 Carrier Frequency O®set Acquisition . . . . . . .11
2.2.2 Carrier Phase Tracking . . . . . . . . . . . . . 12
2.2.3 CFO estimation and compensation structure . . . .14
2.3 E®ect of Clock Offset . . . . . . . . . . . . . . .14
2.4 Clock Offset Synchronization . . . . . . . . . . . 16
2.4.1 Clock Offset Estimation . . . . . . . . . . . . .16
2.4.2 The compensation Method . . . . . . . . . . . . .17
2.5 The Proposed Estimation and Compensation Scheme . .18
2.5.1 CFO estimation and compensation . . . . . . . .. 19
2.5.2 Least Squares Algorithm . . . . . . . . . . . . .23
2.5.3 Post-FFT Phase Compensator . . . . . . . . . . . 24
3 Simulation and Performance 29
3.1 Introduction to IEEE802.11a Standard . . . . . . . 29
3.1.1 IEEE802.11a basic . . . . . . . . . . . . . . . .29
3.1.2 PLCP preamble . . . . . . . . . . . . . . . . . 31
3.1.3 Pilot subcarriers . . . . . . . . . . . . . . . .32
3.1.4 Transmit Center Frequency Tolerance . . . . . . .33
3.1.5 Symbol Clock Frequency Tolerance . . . . . . . . 33
3.2 Simulation Platform . . . . . . . . . . .. . . . . 33
3.3 Channel Model . . . . . . . . . . . . . . . . . 35
3.3.1 Multipath Fading Channel Model . . . . . . . . . 35
3.3.2 Carrier Frequency Offset Model . . . . . .. . . .37
3.3.3 Clock O®set Model . . . . . . . . . . . . . . . .38
3.4 Performance . . . . . . . .. . . . . . . . . . . . 39
3.4.1 Carrier Frequency Estimation . . . . . . . . . . 39
3.4.2 Remaining CFO tracking . . . . . . . . . . . . . 40
3.4.3 Clock Offset Compensation . . . . . . . . . . . .43
3.4.4 System Performance . . . . . . . . . . . . . . . 46
4 Hardware Implementation 48
4.1 Fixed Point simulation . . . . . . . . . . . . . . 48
4.2 Architecture of CFO Acquisition . . . . . . . . . 50
4.2.1 Arc-tangent . . . . . . . . . . . . . . . . . . 54
4.2.2 Sine and Cosine . . . . . . . . . . . . . . . . 55
4.3 Architecture of Phase Recovery . . . . . . . . . . 56
4.4 Hardware synthesis . . . . . . . . . . . . . . . . 57
4.5 IEEE802.11a PHY receiver . . . . . . . . . . . . . 59
4.6 Hardware Improvement . . . . . . . . . . . . . . . 60
5 Conclusion and Future Work 62

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