臺灣博碩士論文加值系統

以絕緣層上履矽為製程平台的技術在此篇論文中，針對室溫結晶技術、先進金屬矽化物模組以及單晶矽鍺/矽基板所製成金氧半穿透式二極體加以研究。第一部分談到的是有關低溫結晶技術。利用電子束在室溫下的結晶法已經證實可以有效將非晶矽結晶化使其晶相轉為複晶矽，且其各種特性優異足以應用在複晶矽電晶體的製程。相較於傳統爐管的高溫耗時結晶過程，電子束的結晶法僅需較少的熱能便可達成，甚至可以在沒有加熱基板的條件下完成結晶化。除此之外，電子束的結晶法所製成之複晶矽電晶體特性亦優於傳統爐管所製成的元件。包括更低的臨界電壓、次臨界區反應率、更高的電子遷移率及更大的元件開關比。雖然在結晶技術上還有其他方法：諸如近來廣被研究的激光雷射退火結晶法，但牽涉到閘極氧化層耐用度的晶粒平坦度仍以電子束的結晶法所製成之複晶矽較佳。除此之外，電子束退火的效能非常好，以致整個製程可以在室溫下進行數分鐘便告完成。此項技術的提出非僅可應用於平面顯示器的多晶矽薄膜電晶體，應用在高結晶度的絕緣層上矽材更是它的另一項有利的發展因素，其良好的電性和簡單快速的低溫製程大大的提高了電子束退火技術在結晶技術上的價值。
第二部分談到先進金屬矽化物模組。以超大型積體電路0.18mm以下製程最為人接受的鎳矽化合物及鈷矽化合物作為研究對象，分別在高界電常數材料:氧化鑭上形成的全金屬矽化閘極與高頻應用的單晶矽鍺/係基板上的金屬矽化作特性研究。在全金屬矽化閘極的N-型及P-型金氧半電晶體表現上，攝氏九百度形成的鈷矽化合物閘疊在十五埃氧化鑭上會有大量的漏電流。這大電流的來源有可能因為在攝氏九百度如此的高溫下，鈷元素過度擴散進入矽基材所造成。然而，以攝氏四百度所製成的全鎳矽化金屬矽化閘極在電壓1伏特的偏壓下卻僅有0.2毫安培/平方公分，如此小的漏電流密度與鋁電極相當。由全鎳矽化金屬矽化閘極所制成的N-型及P-型金氧半電晶體，萃取出來的功函數是4.42電子伏特、臨界電壓分別為0.12和 -0.70 V、電子遷移率和電洞遷移率與未氫化的氧化鉿電晶體差不多，分別為156 和 44平方公分/伏特-秒。在金屬矽鍺化合物的特性上，鎳及鈷與矽鍺的化合物表現也有不同。鎳矽鍺化合物不管在P+N或N+P接面都能低到4-6歐姆/方格的片電阻，這要比起鈷矽鍺化合物的片電阻小多了。此外，鎳矽鍺化合物在P+N或N+P接面，接面漏電流密度都可以小到3´10-8安培/平方公分及 2´10-7安培/平方公分。如此好的特性應該歸因於非常平整的鎳矽鍺化合物層。
此論文的第三部分則關於可應用於光纖通訊及晶片內信號連接線發射源的發光二極體，而此二極體的特點在於它是利用單矽或單晶矽鍺/矽基材所完成的。當然好處就是此種製程方法與技巧可以同時兼顧發光材質成本與現今超大型積體電路製程的相容性。我們將一般的氧化矽，氧化鋁和氧化鋁/氧化銦銻超晶格的結構方式分別在矽基材上做成穿透式金氧半二極體，並對其發出的光加以比較。2.3奈米厚的氧化鋁穿透式金氧半二極體的發光強度比氧化矽穿透式金氧半二極體或0.18mm金氧半電晶體的強度高出了一個數量級，而以三層2奈米-氧化銦銻/1.5奈米-氧化鋁構成的超晶格所製成的穿透式金氧半二極體的發光強度比2奈米-氧化矽穿透式金氧半二極體更是高過三個數量級。其中以超晶格所製成的穿透式金氧半二極體不但有效克服非直接能隙材質在發光上的限制更是將光譜峰值由紅外推入可見光範圍。然而依應用的不同，光譜峰值並不一定要在可見光範圍。以光纖通訊的應用來講，波長在1.3mm及1.55mm的光是衰減最小的，因此利用不同鍺含量的矽鍺化合物再搭配原來使用在矽基材上的氧化銦銻/氧化鋁超晶格結構便可達到。由實驗結果發現，當鍺含量達七成時，穿透式金氧半二極體所發的光便是1.3mm；且由於此波段與矽能隙的波段錯開，意味著甚至可以使用傳統的複晶矽做為二極體的正極，使在此方法在超大型積體電路製程的整合可能性增加。

In this work, the techniques of room temperature crystallization, advanced silicide, and SiGe/Si MOS tunneling diode have been studied. The first topic was regarding the crystallization. Electron-beam crystallization at room temperature for poly-Si thin-film transistor was applied and discussed. In contrast to the high crystallization temperature and long duration of conventional furnace crystallization, electron-beam crystallization could be performed at a low thermal budget even without substrate heating. It also provides better device characteristics than conventional furnace annealing, including smaller threshold voltage, higher mobility, smaller subthreshold swing, and larger ION/IOFF ratio. The much smoother surface than excimer laser annealed sample is also important for further gate oxide integrity and device performance improvement.
The second part discusses the NiSi or CoSi2 characterization and its applications as a gate electrode as well as germano silicide. We have fabricated the fully silicided NiSi on La2O3 for n- and p-MOSFETs. For 900 oC fully silicided CoSi2 on La2O3 gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2×10-4 A/cm2 at 1 V is measured for 400 oC formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm2/V-s obtained by n- and p-MOSFETs are comparable with the HfO2 MOSFETs without using H2 annealing. The Ni and Co germano-silicide on Si0.3Ge0.7/Si have also different behavior. The Ni germano-silicide shows a low sheet resistance of 4-6 W/? on both P+N and N+P junctions, which is much smaller than Co germano-silicide. Besides, small junction leakage currents of 3´10-8 A/cm2 and 2´10-7 A/cm2 are obtained for Ni germano-silicide on P+N and N+P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.
The third part is related to the optical communication realization on single crystalline SiGe/Si substrate. We have compared the electroluminescence of SiO2 tunnel diode, Al2O3 tunnel diode, and Al2O3/ITO superlattice tunnel diode on Si. The electroluminescence intensity of 2.3nm Al2O3 tunnel diode is more than one order of magnitude higher than 2nm SiO2 tunnel diode or 0.18mm MOSFET, while the electroluminescence intensity of 3 periods 20Å-ITO/15Å-Al2O3 superlattice tunnel diode has three orders of magnitude larger than 20Å SiO2 tunnel diode. By Al2O3/Si1-xGex MOS tunnel diodes on Si scheme, we have fabricated SiGe/Si LED with emitting light at around 1.3 mm, for x = 0.7. The emitted photon energy is smaller than the bandgap energy of Si, thus avoiding strong light absorption by the Si substrate. The optical device structure is compatible with that of a MOSFET, since a conventional doped poly-Si gate electrode will be transparent to the emitted light. Increasing the Ge composition from 0.3 to 0.4 only slightly decreases the light emitting efficiency.

ABSTRACT i
ACKNOWLEDGMENTS vii
CONTENTS ix
FIGURE CAPTIONS xii
TABLE CAPTIONS xvi
CHAPTER 1 INTRODUCTION 1
1.1 Crystallization technology 1
1.2 High-k dielectrics 4
1.3 Metal gated MOSFETs 6
1.4 Ni germano silicide 8
1.5 MOS tunneling diodes 12
CHAPTER 2 E-BEAM CRYSTALLIZATION IN ROOM TEMPERATURE 13
2.1 Poly-Si Thin-Film Transistors Crystallized By Electron Beam Annealing 13
2.1.1 Motivation 13
2.1.2 Experiment 14
2.1.3 Results and discussions 16
2.1.4 Conclusion 22
CHAPTER 3 FULLY NiSi GATE AND Ni GERMANO SILICIDE 23
3.1 Fully Silicided NiSi Gate On La2o3 MOSFETs 23
3.1.1 Motivation 23
3.1.2 Experiment 24
3.1.3 Results and discussions 25
3.1.4 Conclusion 31
3.2 Formation Of Ni Germano-Silicide On Single Crystalline Si0.3Ge0.7/Si 32
3.2.1 Motivation 32
3.2.2 Experiment 33
3.2.3 Results and discussions 36
3.2.4 Conclusion 40
CHAPTER 4 SiGe/Si MOS TUNNELING DIDOE WITH 0.7mm ~1.3 mm WAVELENGTH
4.1. Electroluminescence in Al2O3 tunnel diode and Al2O3/ITO superlattice tunnel diode on Si 41
4.1.1 Motivation 41
4.1.2 Experiment 42
4.1.3 Results and discussions 44
4.1.4 Conclusion 50
4.2 Light emission near 1.3 mm using Al2O3/Si0.3Ge0.7/Si tunnel diodes 50
4.2.1 Motivation 51
4.2.2 Experiment 52
4.2.3 Results and discussions 53
4.2.4 Conclusion 58
CHAPTER 5 CONCLUSION AND FUTURE WORKS 59
5.1 Conclusion 59
5.2 Future Work 62
REFERENCES 64
AUTOBIOGRAPHY 83
PUBLICATION LISTS 86

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[3.1.18] Y. H. Lin, F. M. Pan, Y. C. Liao, Y. C. Chen, I. J. Hsieh, and A. Chin, “The Cu contamination effect in oxynitride gate dielectrics,” J. Electrochem. Soc., vol. 148, no. 4, G627 -G629 (2001).
[3.1.19] B. C. Lin, Y. C. Cheng, A. Chin, T. Wang, and C. Tsai, “The Deuterium Effect on SILC,” in 30th Solid State Devices and Materials (SSDM), 1998, pp. 110-111.
[3.2.1] Y. H. Wu and A. Chin, “High temperature formed SiGe p-MOSFETs with good device characteristics,” IEEE Electron Device Lett. vol. 21, no. 7, pp. 350-352, 2000.
[3.2.2] Y. H. Wu, A. Chin, and W. J. Chen, “Thickness dependent gate oxide quality of thin thermal oxide grown on high temperature formed SiGe,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 289-292, 2000.
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[3.2.13] Y. Taur and T. K. Ning, Fundamentals of modern VLSI devices, pp. 196, Cambridge University Press, 1998.
[4.1.1] A. Verma, A. Chatterjee, B. Bhuva, E. D. Jansen, “All Si-based optical interconnect for signal transmission,” Proc. of International Interconnect Technology Conf., pp. 69-72, 2001.
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[4.1.5] A. Chin, M. Y. Yang, C. L. Sun, and S. Y. Chen, “Stack gate PZT/Al2O3 one transistor ferroelectric memory,” IEEE Electron Device Lett. 22, 336-238 (2001).
[4.1.6] Y. Taur and T. K. Ning, Fundamental Modern VLSI Devices, p.195.
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[4.2.6] A. Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high-k Al2O3 gate dielectric with good mobility and low Dit,” in Symp. on VLSI Tech., 1999, pp. 133-134.
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[4.2.9] Y. H. Wu and A. Chin, “High temperature formed SiGe p-MOSFETs with good device characteristics,” IEEE Electron Device Lett., vol. 21, no. 7, pp. 350-352, 2000.
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