臺灣博碩士論文加值系統

本篇論文的主旨在於闡述射頻發射器前置電路的設計方法及製作技術。論文中包含下列三個主要部分﹕（一）一個互補式金氧半、10億赫茲頻帶範圍、使用定電流及電流重複使用技術的電壓控制振盪器，此電壓控制振盪器具有高精準度正交相位輸出和低功率消耗的特性﹔（二）一個互補式金氧半、2伏特、和低功率消耗的直接轉換正交調變器，此調變器整合了正交相位輸出的電壓控制振盪器和射頻放大器，主要應用於10億赫茲頻帶範圍的射頻發射器﹔（三）一個互補式金氧半、低功率消耗、和直接轉換的發射器，此發射器整合了電壓控制振盪器、正交調變器及功率放大器。
首先，本論文設計了一個新的且具有同相和正交相位輸出之互補式金氧半電壓控制振盪器，此電路特色是由一個具有電感電容並聯負載的差動定電流環型振盪電路所架構出來，整個電路完全整合在標準的0.5微米雙層多晶矽雙層金屬之互補式金氧半製程上。在所實現的正交相位輸出之電壓控制振盪器上，當控制電壓從1.5伏特變化至3伏特，輸出振盪頻率可由16.5億赫茲變化至17.73億赫茲共1.23億赫茲的頻率調整範圍。當中心振盪頻率設定為17.28億赫茲，其單邊頻譜相位雜訊在10萬赫茲和100萬赫茲的位移頻率分別為-94分貝載波功率譜密度(dBc/Hz) 和-110分貝載波功率譜密度。由於二級環型振盪器之架構的引用，正交相位輸出之電壓控制振盪器的有效相位誤差小於1.55度。電流重複使用技術的應用，使此電路在3伏特電源供應電壓下，只消耗掉11.6毫安培的工作電流。整個正交相位輸出之電壓控制振盪器晶片，只耗掉260微米乘620微米的晶片面積，其中二個方的螺旋形電感佔掉大部份面積。
其次，本論文中提出了一個互補式金氧半、2伏特、和低功率消耗的直接轉換正交調變器，此調變器整合了正交相位輸出的電壓控制振盪器和射頻放大器，主要應用於10億赫茲頻帶範圍射頻發射器。當同相(I)通道及正交(Q)通道的基頻訊號和具有正交相位的本地振盪分別被加入到一組混合器，正交調變功能即可被實現。由於電流重複使用的技術被使用在正交調變器、具有正交相位輸出的電壓控制振盪器和射頻放大器，因此此晶片具有極低的功率消耗。因為此正交調變器在正電源供應電壓和地之間只串接二個電晶體和一個電阻，所以電源供應電壓可以低至1.5伏特。此正交調變器最主要是設計給19億赫茲歐規數位無線電話發射器應用。整個實驗晶片完全整合在標準的0.35微米N井(N-well) 雙層多晶矽三層金屬之互補式金氧半製程上。此發射器晶片在2伏特工作電壓下，只消耗18毫瓦特的功率。晶片上的電壓控制振盪器在不用任何相位調整及微調，即可提供高精確的正交相位輸出。此電壓控制振盪器在2伏特電源供應電壓下的頻率調整範圍從18.8億赫茲到20.16億赫茲共2.8億赫茲。由於二正交相位的路徑相當匹配，上緣頻帶的主訊號在20億赫茲及2伏特電源供應電壓下，影像拒斥比小於-40.4分貝(dB)，本地振盪漏損量為-47.5分貝載波(dBc)，二階及三階的失真皆小於-47.6分貝載波。當電源供應電壓為3伏特，影像拒斥比會比-51分貝小。
最後，本論文介紹了一個互補式金氧半、低功率消耗、和直接轉換的發射器，其中整合了電壓控制振盪器、正交調變器及功率放大器。此發射器晶片在2.5伏特工作電壓下，只消耗45毫安培的電流。由於電流重複使用技術被使用在正交調變器和具有正交相位輸出的電壓控制振盪器，因此此晶片具有極低的功率消耗。此電壓控制振盪器在0伏特至2.5伏特的控制電壓下，頻率調整範圍從26億赫茲到29.8億赫茲共3.8億赫茲。實驗晶片完全整合在標準的0.25微米單層多晶矽五層金屬及低阻值基體之互補式金氧半的製程上。由於使用高線性正交調變器及低相位誤差的正交相位輸出之電壓控制振盪器，量測到的本地振盪漏損量、影像拒斥比、二階及三階的失真分別為-48分貝載波、53.6分貝、-49.5分貝載波和-43.4分貝載波。針對短距離無線通訊應用，此晶片亦整合了三級的功率放大器，此功率放大器在9.75分貝毫瓦的輸出功率下，具有百分之十五點一的汲極效率。
經過模擬和實驗證實，本論文中所研發的電路將可應用於一個高整合度、全互補式金氧半製程的無線通訊統之中。如此將可以實現一個低價格、小體積的行動通訊裝備。在未來將針對其他的射頻元件做進一步整合，而成為一個完整的收發器。

In this thesis, the design methodology and implementation techniques of CMOS RF transmitter front-end circuits are presented. There are three parts in this research, including: (1) a low-power high-phase-accuracy gigahertz-range CMOS quadrature voltage-controlled oscillator (VCO) with constant-current operation and current-reusable structure; (2) a 2 V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for gigahertz RF transmitter applications; (3) the design and analysis of a CMOS low-power direct-conversion transmitter with integrated VCO and power amplifier.
At first, a new CMOS VCO with both in-phase (I) and quadrature-phase (Q) outputs was designed featuring a constant-current ring oscillator with LC-tank loads. This proposed quadrature VCO is fully integrated in a standard 0.5 mm double-poly-double-metal (DPDM) CMOS technology. The output oscillation frequency was varied from 1.65 to 1.773 GHz having a tuning range of 123 MHz when the controlled voltage changes between 1.5 and 3 V. As the center oscillation frequency is adjusted at 1.728 GHz, phase noises of -94 dBc/Hz and -110 dBc/Hz were obtained for single sideband with offset being set at 100 kHz and 1 MHz from the carrier’s frequency respectively. Due to the application of two-stage ring oscillator, phase error of fabricated quadrature VCO is less than 1.55°. The operation current of 11.6 mA was consumed under a 3 V power supply because of the implementation of current-reused method. This prototype quadrature VCO chip consumes area of 260 mm ´ 620 mm only, with most of it being occupied by two integrated rectangular spiral inductors.
Secondly, a compact low-voltage low-power CMOS direct-conversion quadrature modulator with integrated quadrature VCO and RF amplifier for wireless transmitter applications is proposed and analyzed. By applying both baseband input signals with quadrature phases and quadrature LO signals to a set of combiners, the quadrature modulation functions can be implemented. The low-power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Because only two transistors and one resistor are cascoded in the critical path of the proposed quadrature modulator between power supply and ground, the supply voltage can be as low as 1.5 V. The proposed circuit structure is used to design a quadrature modulator chip for 1.9 GHz DECT transmitter applications. The experimental chip is fabricated by using 0.35 μm N-well double-poly-triple-metal (DPTM) CMOS technology. The power dissipation is only 18 mW under 2 V power supply voltage. The on-chip quadrature VCO can provide highly accurate quadrature signals without any phase tuning or trimming. The frequency tuning range of the quadrature VCO is 280 MHz from 1.88 to 2.16 GHz at 2 V supply voltage. Due to small mismatch among quadrature signal paths, the measured image ratio is below -40.4 dBc under 2 V supply voltage when the desired upper sideband is set at 2 GHz and -51 dBc under 3 V supply voltage when the desired upper sideband at 1.94 GHz. At 2 V supply voltage, the measured LO leakage is -47.5 dBc. Moreover, the measured second-order distortion and third-order distortion are less than -47.6 dBc.
Finally, a CMOS low-power direct-conversion transmitter with integrated VCO and power amplifier is presented in this thesis. The experimental chip of the proposed transmitter is designed and fabricated in 0.25 μm single-poly-five-metal (1P5M) CMOS process with low-resistivity substrate. The transmitter chip drains only 45 mA from a 2.5 V power supply voltage. The low-power feature of transmitter chip is furnished by the current reuse technique used among quadrature modulator and quadrature VCO. The 380 MHz tuning range of the realized quadrature VCO can be varied from 2.6 to 2.98 GHz while controlled voltage changes between 0 and 2.5 V. With highly linear quadrature modulator and low phase error quadrature VCO structure, the measured LO leakage, image rejection, second-order distortion and third-order distortion of the modulated signal at the output of transmitter achieve -48 dBc, 53.6 dB, -49.5 dBc, and -43.4 dBc, respectively. The three-stage power amplifier is also integrated to provide 9.75 dBm output power with 15.1% overall efficiency for short-range wireless communications.
It is believed that the proposed high performance RF transmitter front-end circuits can be applied to an all-CMOS wireless communication system. Thus a low-cost small-size mobile equipment can be implemented. Further research on the integration of other transceiver components will be conducted in the future.

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) iv
ACKNOWLEDGEMENT vii
CONTENTS ix
TABLE CAPTIONS xii
FIGURE CAPTIONS xiv
CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND 1
1.2 REVIEW ON TRASNMITTER ARCHITECTURES AND BULIDING BLOCKS 2
1.2.1 Transmitter Architectures 2
1.2.1.A Superheterodyne Transmitter 2
1.2.1.B Direct-Conversion Transmitter 3
1.2.2 Building Blocks 4
1.2.2.A Quadrature VCO 4
1.2.2.B Quadrature Modulator 6
1.2.2.C Power Amplifier 6
1.3 ORGANIZATION OF THIS THESIS 7
CHAPTER 2 A CMOS QUADRATURE VCO WITH CONSTANT-CURRENT OPERATION AND CURRENT-REUSABLE STRUCTURE 14
2.1 INTRODUCTION 14
2.2 OPERATIONAL PRINCIPLE 15
2.3 CIRCUIT DESIGNS 18
2.3.1 The Circuit Design of 1.7-GHz Quadrature VCO 19
2.3.2 The Simulation Results of 5.3-GHz Quadrature VCO 21
2.3.3 Layout Consideration 22
2.4 EXPERIMENTAL RESULTS 24
2.5 SUMMARY 29
CHAPTER 3 A CMOS DIRECT-CONVERSION QUADRATURE MODULATOR WITH INTEGRATED QUADRATURE VCO AND RF AMPLIFIER FOR DECT 55
3.1 INTRODUCTION 55
3.2 OPERATIONAL PRINCIPLE 57
3.3 CIRCUIT DESIGNS 61
3.3.1 Quadrature Modulator 61
3.3.2 Merged Quadrature VCO 66
3.3.3 Merged RF Amplifier 67
3.3.4 Overall Circuit 69
3.4 EXPERIMENTAL RESULTS 70
3.5 SUMMARY 74
CHAPTER 4 A COMPACT CMOS DIRECT-CONVERSION TRANSMITTER FOR BLUETOOTH 101
4.1 INTRODUCTION 101
4.2 OPERATIONAL PRINCIPLE 103
4.3 CIRCUIT DESIGNS 105
4.3.1 Quadrature Modulator 105
4.3.2 Quadrature VCO 108
4.3.3 Power Amplifier 110
4.4 EXPERIMENTAL RESULTS 111
4.5 SUMMARY 117
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 156
5.1 MAIN RESULTS OF THIS THESIS 156
5.2 FUTURE WORKS 158
REFERENCES 161
VITA 176
PUBLICATION LIST 177

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