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研究生:黃志翔
研究生(外文):ChihHsiang Huang
論文名稱:場效電晶體高頻模型的建立及矽鍺合金層應用於高介電物質電晶體對電洞遷移率的改善
論文名稱(外文):RF MOSFET modeling and the improvement of hole mobility of the SiGe high-k PMOSFET
指導教授:荊鳳德
指導教授(外文):Albert Chin
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:87
中文關鍵詞:場效電晶體矽鍺合金層高介電係數物質電洞遷移率
外文關鍵詞:MOSFETSiGe layerHigh-k dielectrichole mobility
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互補式金氧半場效電晶體具有價格便宜、整合性高的優點,因此在一些需要較低功率的射頻電路中,有極高的潛力取代高價的三五族製程。對於電路設計者來說,正確的場效電晶體高頻模型對於電路是十分地重要的。從我們建立的模型中,可以成功地預測閘極長度從0.18m到0.13m的射頻電晶體的S參數及雜訊特性,另外,我們也研究了不同元件佈局對於高頻電晶體相關特性的影響,並且發現在某個元件佈局時,可以達到最低的雜訊,這對於低雜訊放大器設計的元件選擇是重要的。在電晶體不斷地微縮時,我們必須使用高介電係數物質來降低元件關閉時的功率以及增加電晶體的電流驅動力,因為高介電係數的使用,將會降低通道電子電洞的載子遷移率。不過在高頻電晶體中,載子的遷移率對於電晶體的操作速度有極大的影響。我們使用了矽鍺非應力層的方法來提升電洞的遷移率。利用我們的方法,可以製作出不同鍺含量的單晶矽鍺非應力層,而且有很平整的表面。另外,從漏電流和電容電壓的曲線圖,以及可靠度測試的資料中,我們可以發現我們的高介電係數氧化層的品質十分良好。從汲極電流特性中,我們可以發現矽鍺的P型電晶體有兩倍於矽標準電晶體的驅動力,另外也可以將電洞的遷移率提高1.8倍,有效解決將高介電物質導入未來VLSI技術所遇到的瓶頸。

Because CMOS has advantages of low-cost and highly integrity, it has potential to replace the III-V device in low-power front-end circuit. In the respect of circuit designer, the accurate model is important for circuit performance. In our universal model, we can successfully predict the S-parameter and noise characteristic. In addition, we also study the layout dependent characteristic of RF MOSFET. The optimized finger numbers with optimized noise can be found in both 0.18μm and 0.13μm NMOSFET, which is essential for low noise amplifier designer. Besides, to continuously scale down the dimension of MOSFET, it is unavoidable of using high- dielectric to reduce gate leakage current and improve current drive capability. When applying high-dielectric, it also degrades the carrier mobility. The operation frequency of RF MOSFET is highly dependent on carrier mobility. We use novel strain-relaxed Si0.3Ge0.7 channel device to improve hole mobility. In our study, we have successfully fabricated single crystalline with different Ge content and smooth surface. As can be seen in leakage current density, C-V characteristic and reliability test of PMOSFET, we found the quality of high-and SixGe1-x layer is good. We can also improve the current drive capability and hole mobility to 2 times higher and 1.8 times higher than Si control device. We can efficiently overcome the problems when introducing high- dielectric into VLSI technology.

Chapter 1 Introduction
1.1 Motivation ……………...………………………………………………………... 1
1.2 The Si RF Technology.……………………………………………………………2
1.3 The Si1-xGex Layer….……………………………………………………………..8
1.4 The High- dielectric …………………………...……………………………….12
1.5 Innovation and Contribution …………………………………………………….16
Chapter 2 RF noise in 0.18 m and 0.13 m MOSFETs
2.1 Introduction.....………………………………………………………………… 24
2.2 Experimental..…………………………………………………………………. 25
2.3 Results and Discussion ………………………………………………………... 26
2.4 Conclusion …………………………………………………………………….. 29
Chapter 3 Characterization of Si/SiGe heterostructures on Si formed by solid phase reaction
3.1 Introduction …………………………………………………………………… 35
3.2 Experiment ……………………………………………………………………. 36
3.3 Results and Discussion ………………………………………………………... 37
3.4 Conclusion …………………………………………………………………….. 40
Chapter 4 Device level characterization of conduction-band barrier height and energy bandgap of strain-relaxed SiGe
4.1 Introduction …………………………………………………………………… 47
4.2 Experiment ……………………………………………………………………. 48
4.3 Results and Discussion ………………………………………………………... 49
4.4 Conclusion …………………………………………………………………….. 51
Chapter 5 La2O3/Si0.3Ge0.7 p-MOSFETs with high hole mobility and good device characteristics
5.1 Introduction …………………………………………………………………… 57
5.2 Experiment ……………………………………………………………………. 58
5.3 Results and Discussion ………………………………………………………... 59
5.4 Conclusion …………………………………………………………………….. 61
Chapter 6 Conclusions
Reference …………………………………………………………………………..68

Chapter 1
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[1.5] Robert J. P. Lander, Youri V. Ponomarev, Jurgen G. M. van Berkum, and Wiebe B. de Boer, “High Hole Mobilities in Fully-Strained Si1-xGex Layers (0:3 < x < 0:4) and their Significance for SiGe pMOSFET Performance,” IEEE Trans. Electron Devices. vol. 48, no. 8, pp.1826-1832, Aug 2001.
[1.6] E. Morifuji, H. S. Momose, T. Ohguro, T. Yoshitomi, H. Kimijia, F. Matsuoka, M. Kinugawa, Y. Katsumata, and H. Iwai, “Future perspective and scaling down roadmap for RF CMOS,” in Symp. on VLSI circuit Dig., pp.165-166, June 1999.
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Chapter 2
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Chapter 3
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Chapter 4
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Chapter 5
[5.1] Y. H. Kim, C. H. Lee, T. S. Jeon, W. P. Bai, C. H. Choi, S. J. Lee, L. Xinjian, R. Clarks, D. Roberts, and D. L. Kwong, “High quality CVD TaN gate electrode for sub-100nm MOS devices,” in IEDM Tech., Dig., 2001, pp. 667-670.
[5.2] K. Oishi, C. S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, E. Dharmarajan, and J. C. Lee, “Reliability characteristic, including NBTI, of polysilicon gate HfO2 MOSFET’s,” in IEDM Tech., Dig., 2001, pp. 659-662.
[5.3] D. A. Buchanan, E.P. Gusev, E. Cartier, H. Okorn-Schmidt, K. Rim, M. A. Gribelyuk, A. Mocuta, A. Ajmera, M. Copel, S. Guha, N. Bojarczuk, A. Callegari, C. D’Emic, P. Kozlowski, K. Chan, R. J. Fleming, P.C. Jamison, I. Brown, and R. Arndt, “80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications,” in IEDM Tech., Dig, 2000, pp. 223-226.
[5.4] Chin, C. C. Liao, C. H. Lu, W. J. Chen, and C. Tsai, “Device and reliability of high-k Al2O3 gate dielectric with good mobility and low Dit,” in Symp. on VLSI Tech.,1999, pp. 135-136.
[5.5] Chin, Y. H. Wu, S. B. Chen, C. C. Liao, W. J. Chen, “High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5-10Å,” in Symp. on VLSI Tech.,2000, pp. 16-17.
[5.6] Y. Taur and T. K. Ning, Fundamentals of Modern VLSI Devices, Cambridge, U.K.: Cambridge Univ. Press, 1998, p. 286.
[5.7] S. Verdonckt-Vandebroek, E. F. Crabbe, B. S. Meyerson, D. L. Harame, P. J. Restle, J. M. C. Stork, and J. B. Johnson, “SiGe-channel heterojunction p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, no. 1, pp. 90-101, 1994.
[5.8] R. S. Prassad, T. J. Thornton, S. Kanjanachuchai, J. Fernandez, and A. Matsumura, “Mobility degradation in gated Si: SiGe quantum wells with thermally grown oxide,” Electron Lett., vol. 31, no. 21, pp. 1876-1878, 1995.
[5.9] K. Goto, J. Murota, T. Maeda, R. Schutz, K. Aizawa, R. Kircher, K. Yokoo, and S. Ono, “Fabrication of a Si1-xGex channel metal-oxide-semiconductor field-effect transistor (MOSFET) containing high Ge fraction layer by low-pressure chemical vapor deposition,” Jpn. J. Appl. Phys., vol. 32, no. 1B, pp. 438-441, 1993.
[5.10] Y. H. Wu, W. J. Chen, A. Chin, and C. Tsai, “The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si,” Appl. Phys. Lett., vol. 74, no. 4, pp. 528-530, 1999.
[5.11] Y. H. Wu and A. Chin, “High temperature formed SiGe p-MOSFETs with good device characteristics,” IEEE Electron Device Lett., vol. 21, no. 7, pp. 350-352, 2000.
[5.12] Y. H. Wu and A. Chin, “Gate oxide integrity of thermal oxide grown on high temperature formed Si0.3Ge0.7,” IEEE Electron Device Lett., vol. 21, no. 3, pp. 113-115, 2000.
[5.13] Y. H. Wu, A. Chin, and W. J. Chen, “Thickness dependent gate oxide quality of thin thermal oxide grown on high temperature formed SiGe,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 289-291, 2000.
[5.14] Y. Lin, W. J. Chen, C. H. Lai, A. Chin, and J. Liu, “Formation of Ni germano-silicide on single crystalline Si0.3Ge0.7/Si,” IEEE Electron Device Lett. vol. 23, no. 8, pp. 464-466, 2002.
[5.15] Salm, J. H. Klootwjik, Y. Ponomarev, P. W. M. Boos, D. J. Gravestejin, and P. H. Woerlee, “Gate current and oxide reliability in p+ poly MOS capacitors with poly-Si and poly-Si0.7Ge0.3,” IEEE Electron Device Lett., vol. 19, no. 7, pp. 213-215, 1998.

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