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研究生:謝坤宏
論文名稱:微小化面積里德-所羅門解碼器之設計與實現
論文名稱(外文):Design and Implementation of Small-Area Reed-Solomon Decoder
指導教授:李程輝
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
中文關鍵詞:里德-所羅門解碼器錯誤位置多項式有限場乘法器錯誤多項式更新方塊
外文關鍵詞:Reed-Solomondecodererror location polynomialfinite field multipliererror location update block
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在本篇論文當中,我們提出了一個微小化面積的里德-所羅門(Reed-Solomon)解碼器架構。對於t個改錯能力的里德-所羅門碼,我們只需使用t+1個有限場(finite field)乘法器即可完成inversionless Berlekamp-Massey演算法當中的錯誤位置多項式(error location polynomial)運算,相較於其他相關的研究,此一設計可以節省30%至80%的面積。將此一架構最佳化之後,關鍵路徑(critical path)為一個有限場乘法器加上一個有限場加法器再加上兩個雙埠多工器(2×1 multiplexer)。在TSMC的0.25μm製程與SYNOPSYS軟體下的模擬環境下,我們針對(255,239) 里德-所羅門碼所合成出來的錯誤多項式更新方塊(error location update block)只需要16043個邏輯閘。並且在Debussy軟體中的波形模擬環境下,錯誤多項式更新方塊可在274Mhz的運作時脈下正確運作。
This paper presents a small-area architecture for Reed-Solomon decoder. For t error correct capability Reed-Solomon code, the architecture just needs t+1 finite field multiplier for error location polynomial computation, which is base on inversionless Berlekamp-Massey algorithm. Compare with other research about Reed-Solomon decoder, this architecture will save 30% to 80% area. The critical path of this architecture passes through one finite field multiplier, one finite field adder, and two 2x1 multiplexer. For (255,239) Reed-Solomon code, the complexity of the error location update block reported by synthesis tool in SYNOPSIS was 16043 gates in TSMC’s 0.25μm CMOS technology. And the error location update block can operate at 274Mhz correctly in Debussy’s waveform simulation tool environment.
中 文 摘 要 ..............................................ⅰ
Abstract .................................................ⅱ
Contents ................................................ ⅲ
List of Tables ...........................................ⅴ
List of Figures ..........................................ⅵ
Chapter 1 Introduction ................................... 1
Chapter 2 Reed-Solomon Code .............................. 3
2.1 Finite Field GF(2m) .................................. 3
2.2 Encoding of Reed-Solomon Code ........................ 5
2.3 Peterson-Gorenstein-Zierler Decoding ................. 7
2.4 Berlekamp-Massey Algorithm .......................... 11
2.5 Inversionless Berlekamp-Massey Algorithm ............ 12
2.6 Forney Algorithm .................................... 13
Chapter 3 Reed-Solomon Encoder .......................... 16
Chapter 4 Reed-Solomon Decoder .......................... 19
4.1 Syndrome Calculator ................................. 20
4.2 Error Location Update Block ......................... 22
4.2.1 Small-Area Architecture for Decoding ...... 22
4.2.2 Finite Field Multiplier ................... 25
4.2.3 Syndrome Provider ......................... 29
4.2.4 Finite State Machine Controller ........... 30
4.2.5 Synthesis Result .......................... 32
4.3 Combined Chien-Search and Forney Block .............. 33
Chapter 5 Summary ....................................... 36
5.1 Efficiency of Our Implementation .................... 36
5.2 Compare with the Fitzpatrick Algorithm .............. 37
5.3 Compare with the RIBM Algorithm ..................... 39
5.4 Compare with the ME Algorithm ....................... 41
5.5 Conclusion .......................................... 42
Reference ............................................... 43
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[2] Irving S. Reed, Xuemin Chen, “Error-Control Coding for Data Networks”. Kluwer Academic Publishers, 1999.
[3] E.M. Popovici, P. Fitzpatrick, “Reed-Solomon Codes for Optical Communications”. Microelectronics, 2002. MIEL 2002. 23rd International Conference on, Volume: 2, 2002. pp.613 — 616.
[4] D.V. Sarwate, N.R. Shanbhag, “High-speed architectures for Reed-Solomon decoders”. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume: 9 Issue: 5, Oct 2001. pp.641 — 655.
[5] H. Lee, “A VLSI design of a high-speed Reed-Solomon decoder”. ASIC/SOC Conference 2001. Proceedings. 14th Annual IEEE International, 2001. pp. 316 — 320.
[6] You Yu-xin, Wang Jin-xiang, Lai Feng-chang, Ye Yi-zheng, “Design and Implementation of High-Speed Reed-Solomon decoder”. Circuits and Systems for Communications 2002. Proceedings. ICCSC ''02. 1st IEEE International Conference on, 2002. pp.146 — 149.
[7] K. Seki, K. Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama, “Single-chip 10.7 Gb/s FEC codec LSI using time-multiplexed RS decoder”. Custom Integrated Circuits, 2001, IEEE Conference on, 2001. pp. 289 —292.
[8] H.C. Chang, C.B. Shung, C.Y. Lee, “A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications”. Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 2 , Feb 2001. pp. 229 — 238.
[9] H. Lee, “An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder”. VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on , 2003. pp. 209 —210.
[10] H.J. Kang, I.C. Park, “A High-Speed and Low-Latency Reed-Solomon Decoder Based on A Dual-Line Structure” Acoustics, Speech, and Signal Processing, 2002. Proceedings. (ICASSP ''02). IEEE International Conference on , Volume: 3 , 2002
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[11] E. Berlekamp, “Algebraic Coding Theory”. New York: McGraw-Hill 1968.
[12] Robert J. McEliece, “Finite Fields for Computer Scientists and Engineers”. Kluwer Academic Publishers, 1987.
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