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研究生:吳兆軒
研究生(外文):Chao-Hsuan Wu
論文名稱:電容式微加速度計之CMOS感測電路之設計、模擬與製作
論文名稱(外文):The Design, Simulation and Fabrication of CMOS Sensing Circuits of Capacitive Micro Accelerometer
指導教授:邱俊誠邱俊誠引用關係
指導教授(外文):Jin-Chern Chiou
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:74
中文關鍵詞:微加速度計感測電路
外文關鍵詞:Capacitive Micro AccelerometerSensing Circuits
相關次數:
  • 被引用被引用:2
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本論文之目的在探討電容式加速度計之感測電路之理論與實際應用。 首先先對電容式加速度計的架構做分析, 接著再介紹目前被廣泛使用在電容感測電路的同步偵測電路及切換式電容電路。 由於雜訊的因素, 這兩種架構在面對電容變化在數百fF或甚至數十fF時並不適用。 因此, 本論文將使用抗雜訊能力較高的CDS架構做為感測電路。 從使用聯電0.5 2P2M 製程之佈局後模擬結果可以看出, CDS感測電路的輸出具有相當高的線性度及靈敏度, 可以感測到0.5 fF 的電容變化。 除此之外, 本論文也用現有之電子元件來實現及驗證CDS架構。
The purpose of this dissertation is to discuss the structure and implementation of CMOS sensing circuits of capacitive micro accelerometer. First, the structure of micro accelerometer will be analyzed. Then we will introduce the synchronous detection and switched-capacitor sensing schemes which are both widely used in capacitive sensing circuits. As a result of the various sources of noises, however, these two sensing schemes will not be suitable for sensing which is in the range of hundreds or even tens of femto-farads. Therefore, the CDS sensing scheme which has higher signal-to-noise ratio is used in this thiese. From the post-simulation results which uses UMC 0.5 2P2M process, the outputs have quite high linearity and sensitivity. The resolution is up to 0.5fF. Moreover, we also use the discrete electronic elements to implement and verify the CDS sensing circuits.
ABSTRACT (CHINESE VERSION) I
ABSTRACT (ENGLISH VERSION) II
ACKNOWLEDGEMENTS III
TABLE OF CONTENTS IV
LIST OF FIGURES VII
LIST OF TABLES IX
CHAPTER 1 INTRODUCTION 1
1.1 OVERVIEW 1
1.2 MOTIVATION 3
1.3 THESIS ORGANIZATION 4
CHAPTER 2 SYSTEM STRUCTURE 5
2.1 INTRODUCTION 5
2.2 CAPACITIVE MICRO ACCELEROMETER 5
2.2.1 BASIC CONCEPTS 5
2.2.2 THE STRUCTURE OF THE MEMS CAPACITOR 6
2.2.3 MEMS CAPACITOR MODELING 9
2.3 CMOS SENSING CIRCUITS 10
2.3.1 CAPACITANCE SENSING TECHNIQUES 10
2.3.2 SYNCHRONOUS DETECTION SCHEME 10
2.3.3 SWITCHED-CAPACITOR SENSING SCHEME 14
2.3.4 SENSING RESOLUTION 16
2.4 SUMMARY 18
CHAPTER 3 NONIDEALITIES IN THE SENSING CIRCUITS 20
3.1 INTRODUCTION 20
3.2 ERRORS IN SWITCHED-CAPACITOR SENSING CIRCUITS 21
3.2.1 AMPLIFIER OFFSET VOLTAGE 21
3.2.2 FLICKER NOISE 21
3.2.3 SWITCH CHARGE INJECTION AND CLOCK FEEDTHROUGH 22
3.2.4 KT/C NOISE 25
3.3 CORRELATED DOUBLE SAMPLING 26
3.3.1 BASIC CONCEPT 26
3.3.2 PRINCIPLE OF OPERATION 26
3.4 SUMMARY 28
CHAPTER 4 CIRCUITS DESIGNING 29
4.1 INTRODUCTION 29
4.2 OPERATIONAL AMPLIFIER 29
4.2.1 BASIC CONCEPT 29
4.2.2 CIRCUITS DESIGNING 31
4.2.3 SIMULATION RESULTS 34
4.3 COMPARATOR 38
4.3.1 BASIC CONCEPT 38
4.3.2 CIRCUITS DESIGNING 39
4.3.3 SIMULATION RESULTS 43
4.4 SWITCH 46
4.4.1 BASIC CONCEPT 46
4.4.2 CIRCUITS DESIGNING 46
4.5 CAPACITOR 48
4.5.1 BASIC CONCEPT 48
4.5.2 CIRCUITS DESIGNING 48
4.6 CLOCK GENERATOR 51
4.6.1 BASIC CONCEPT 51
4.6.2 CIRCUITS DESIGNING 51
4.6.3 MEASUREMENT RESULTS 52
4.7 SUMMARY 52
CHAPTER 5 SIMULATION AND MEASUREMENT RESULTS 54
5.1 INTRODUCTION 54
5.2 SIMULATION RESULTS 54
5.2.1 CDS CV CONVERTER 55
5.2.2 CDS CV CONVERTER WITH DIGITAL OUTPUT 62
5.3 MEASUREMENT RESULTS 65
5.4 SUMMARY 68
CHAPTER 6 CONCLUSIONS 69
6.1 RESULTS AND DISCUSSIONS 69
6.2 FUTURE WORKS 70
REFERENCE 72
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