臺灣博碩士論文加值系統

本論文研究 3V 100MHz 導管式類比數位轉換器(ADC)以TSMC 035um 製程參數之設計模擬。本論文中ADC架構是採用每一級1.5bit共八級和最後一級2bit，此ADC電路包含CMOS全差動取樣保持電路(S/H)，主要應用在高速轉換器的前端。我們利用拔靴帶電路(bootstrapping circuit)以降低電荷注入效應(signal dependent charge injection)，並且利用1.5bit寬共模範圍的數位類比轉換器以減少雜訊(noise)和功率消耗(power consunption)。在 3V電源供應(power supply)100MHz 周期頻率下本轉換器共消耗 269mW。微分和積分非線性誤差(Differential and Integral Nonlinearity, DNL and INL)在MATLAB的模擬下分別為0.73LSB和 LSB。

This thesis describes the design of a 3 V, 100MHz pipeline analog to digital converter (ADC) implemented by simulation with 0.35μm one-poly four-metal process. The ADC consists of eight 1.5-bit stages and the final stage is a 2-bit stage. It consists of CMOS full differential Sample and Hold circuit(S/H), which is mainly intended for front-end use in high speed ADC. Bootstrapping circuit is needed to reduce signal-dependent charge injection, and 1.5bit digital to analog converter (DAC) with wide common mode compliance reduce noise and power consumption. The A/D converter dissipates 269mW at a 100MHz clock rate with 3 V single supply voltage. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.73 LSB and LSB, respectively, by MATLAB simulation.

Abstract…………....………………………………………….i
Table of Contents...…………………………………………..iii
List of Figures………………………………………………...vi
List of Tables………………………………………………….ix
Chapter 1 Introduction ………………………………….1
1.1 Motivation………………………………………………………...1
1.2 Analog and digital interface……………………………................2
1.3 Pipelined A/D converter…………………..………………………4
1.4 Thesis organization………………………………………………..4
Chapter 2 A/D Converter Architecture…………………6
2.1 Introduction ………………………………………………………6
2.2 Classification……………………………………………………...6
2.3 The architectures of nyquest A/D converters……………..………6
2.3.1 Flash architecture…………………….………………………….7
2.3.2 Two-step architecture…………..……...………………………..8
2.3.3 Cyclic architecture…………………….……………………….10
2.3.4 Pipelined architecture…………………….....…………………11
2.3.5 Succesive approximation architecture………..……..……….12
2.3.6 Integrating architecture…………………..……………………13
2.4 The architectures of oversampling A/D converters……...…….14
Chapter3 System Design of the 1.5b/stage pipeline
A/D Converter...……..………….……………..17
3.1 Introduction……………………………………..………..……….17
3.2 Pipeline ADC…………………………...........................................17
3.3 Calibration algorithm for the pipeline dADC…...…………….…..24
3.3.1 Capacitor error-averaging..………………………………....24
3.3.2 Conmutating feedback-capacitor switching algorithm……..27
3.4 1.5-bit / stage pipelined ADC……………..….………………….31
3.4.1 System design………….…………………………………...31
3.4.2 Timing analysis for pipelined ADC………..……………….32
3.4.3 Digital correction logic………………..…….……………..……..35
Chapter 4 Behavioral Model of Pipelined ADC…………36
4.1 Introduction…..……………………………………………..36
4.2 Each block of behavioral model pipelined ADC….…..….…….....36
4.2.1 S/H circuit……..…………….…….………..………………36
4.2.2 1.5 bit flash ADC circuit….…..….…..………..……………37
4.2.3 One stage of pipelined ADC circuit….....….….………...….38
4.2.4 2 bit flash ADC……...…..……….………….……………...40
4.2.5 10 bit pipelined ADC.…….….…..…………..……………..41
4.3 Non-linear effect...………………..……….………………………43
4.3.1 Capacitor mismatch….…....………………………………..43
4.3.2 Comparator offset.........….…………………………………43
4.4 Capacitor and resistor matching…...…………...………………..44
4.5 Summary…………………….…………………………..……….46
Chapter 5 Block Architecture of 1.5 bit Pipeline ADC…..47
5.1 Introduction………………………………….…………..47
5.2 A mismatch Insensitive CMOS dynamic comparator for
pipeline A/D converter......…….………………………………….47
5.3 Low-Power Low-Voltage IC Design………..…………………….49
5.2.1 Reliable high-swing MOS switch…..….………..….………49
5.2.2 Advantage of bootstrapped circuit……..…………..……….52
5.2.3 Low voltage switch-capacitor dsesign issue………...…..….52
5.4 Design flip around bottom plate sampling S/H circuit.......…….…56
5.4.1 Operation of flip around bottom sampling S/H circuit….….57
5.5 The 1.5-bit multiplying DAC (MDAC) circuit……...…………....59
5.5.1 The Conventional MDAC………….………………………61
5.5.2 The 1.5 bit advantage for high speed operation….…….…...65
5.5.3 Noise analysis in pipeline ADC………..…………….....…..67
5.6 Operational amplifier….…….…………………………………….71
5.6.1 Design Issue of Operational Amplifier………………..……72
5.6.2 Telescopic Operational Amplifier Schematic……………....73
5.6.3 Folded Cascode Operational Amplifier…………..………...79
5.7 Clock generator……….…….…………………………….……….85
5.8 Final 2bit ADC simulation……………………………………….86
5.9 Summary…………………………….………………...…..87
Chapter 6 Conclusion...…………………………………..89
References…………………………………….…….91

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