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研究生:吳建賢
研究生(外文):Chien-Hsien Wu
論文名稱:RLC樹狀電路之降階模型
論文名稱(外文):Model Order Reduction for RLC Tree
指導教授:林清安林清安引用關係
指導教授(外文):Ching-An Lin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機與控制工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:53
中文關鍵詞:RLC樹狀電路降階模型
外文關鍵詞:RLC treeModel Order Reduction
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我們提出一種轉移函數係數匹配法--- 以兩個極點一個零點的二階轉移函數近似---來求得數樹狀電路的降階模型,而轉移函數的係數可用KVL所表示的矩陣代入簡易的公式計算出來,我們亦提出明確的公式來計算步階響應的延遲時間、上升時間和最大超越量;由模擬結果得知,我們提出的方法比僅用兩個極點的二階轉移函數近似,更能精確估計系統的性能。我們亦將之前所提出的一些降階方法應用在RLC樹狀電路上並做比較,這些方法分為兩大類--- 轉移函數係數匹配法和奇異值分解法;將模型降為同樣階數的情況下,奇異值分解法會得到較近似的模型,然而,轉移函數係數匹配法的計算複雜度較小。

We propose a two-pole one-zero second-order approximation for
transfer function based on the moment matching method for RLC
trees. Fundamental loop matrix formulation of circuit equations
allows efficient and simultaneous computations of moments at all the nodes. Explicit formulas for step response parameters such as delay time, rise time, overshoot, etc., are given. The simulations show that the method we propose is improved accuracy over existing second-order approximation. We also compare the algorithms that have been proposed by applying them to three examples of RLC trees. The algorithms are separated by two methods--- the moment matching methods and the singular value decomposition (SVD) based methods. The SVD based methods lead to smaller error than the moment matching based methods when we consider the reduced models of the same dimension. But the moment matching based methods are numerically more efficient than the SVD based methods.

Chapter 1: Introduction 1
Chapter 2: Representation of RLC Tree 3
2.1 State Equation of RLC Tree 3
2.2 Transfer Matrix of RLC tree 6
2.3 Moment Computation 9
Chapter 3: Moment Matching Based Methods for Model Order Reduction 12
3.1 Asymptotic Waveform Evaluation 12
3.2 Second-Order Approximation 16
3.2.1 Transfer Function Description 16
3.2.2 Step Response Parameters 17
3.3 Pad\'{e} Approximation via Lanczos Algorithm 20
3.3.1 Unsymmetric Lanczos Based PVL Algorithm 20
3.3.2 Arnoldi Based PVL Algorithm 25
Chapter 4: Singular Value Decomposition Based Methods 28
4.1 Directly Balanced Truncation 28
4.2 Singular Perturbation Approximation 30
4.3 Methods for Reducing Computational Complexity 32
4.3.1 Rabiei's Algorithm 32
4.3.2 Predominant Controllable and Observable Subspaces 35
Chapter 5: Simulation Results 38
Chapter 6: Conclusion} 51
Reference 52

L. Chua, C. Desoer, and E Kuh, Linear and nonlinear circuit, McGraw Hill 1987.
Y. Ismail, E. G. Friedman, and J. Neves,``Equivalent elmore delay for RLC trees,'' in IEEE Trans. Computer-Aided Design of Intergrated Circuits and System, vol.19, pp. 83-97, Jan. 2000.
L. T. Pillage, and R. A. Rohrer,``Asymptotic waveform evaluation for timing analysis,'' in IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, APR. 1990.
F. Feldmann, and R. W. Freund,``Effecient linear analysis by Pad\'{e} approximation via Lanczos process,'' in IEEE Trans. on CAD, vol. 14, No5, pp. 639-649, May 1995.

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