臺灣博碩士論文加值系統

近年來多媒體通訊之蓬勃發展同時也帶動了全球3C產業的急速進步，因而在實際應用上傳統的ASIC系統開發與設計整合已無法跟上其快速的變化與多樣的需求，對系統設計複雜度不斷的提高及Time-To-Market的壓力下，把FPGA及微處理器的核心以軟體或是硬體方式內嵌在同一晶片上，擁有內建可程式化 (Embedded Programmable) 能力的設計，將可提供系統設計之另一出路。
在本篇論文中，建立一SOPC平台式設計之環境應用於多媒體通訊。我們採用Altera APEX 20K200E484-2X之FPGA嵌入Nios CPU並利用軟體方式進行JPEG壓縮的工作，首先將Nios CPU嵌入至現場可程式化邏輯陣列(Field Programmable Gate Array; FPGA)中，並藉由CMOS sensor擷取影像送給嵌入式處理器利用此嵌入式處理器進行JPEG壓縮的動作，隨即透過網路將影像傳送至遠端使用者。在其中，我們完成CMOS sensor擷取影像及網路伺服器環境的架設，並成功的利用嵌入式處理器Nios進行JPEG壓縮的工作，我們使用176 x 104之影像大小進行壓縮的工作，並先將原始影像存放在快閃記憶體 (flash memory) 中，然後嵌入式處理器從快閃記憶體中抓取原始影像資料並將壓縮過的影像存放在SRAM中，以利用乙太網路板將JPEG格式的影像資料流傳送至遠端使用者。使用者可以透過瀏覽器來存取已壓縮過的資料以觀看JPEG之圖像。

The full of vitality multimedia communications development has increased dramatically 3C industry in the world. Therefore practical applications, tradition ASIC system cannot meet the rapidly and vary development and design integrated. However, standard CPU also cannot meet the rapidly application. Since the system design more complexity and time-to-market pressure, the platform-based design methodology has approached.
In this thesis, we develop a SOPC platform-based design environment for multimedia communications. We adopt the Altera APEX20K200E484-2X device. The JPEG compression is performed on software method in the embedded processor. First, we embed a Nios processor in FPGA (Field Programmable Gate Array). Second, we feed the image data with Nios processor by CMOS sensor. The compressed image data transports to client user by Ethernet daughter board. In this task, we successfully complete the JPEG compression by the Nios processor and web server system. The raw image data is stored in the flash memory. Afterward, the embedded processor can be fetched the raw image data from the flash memory. The compressed image data is stored in SRAM memory. The format of the JPEG image will be transformed to the client by the Ethernet daughter board. Eventually, the user can be accessed the compressed image data through by browser.

ABSTRACTI
CHAPTER 1 INTRODUCTION1
1.1MOTIVATION1
1.2PLATFORM-BASED DESIGN OVERVIEW2
1.3THESIS ORGANIZATION4
CHAPTER 2 FUNDAMENTAL CONCEPTS OF JPEG ENCODER SYSTEM5
2.1DCT-BASED JPEG ENCODER ARCHITECTURE6
2.2DISCRETE CONSINE TRANSFORM (DCT)7
2.3QUANTIZATION8
2.4ENTROPY CODING9
2.4.1Huffman Coding of the DC Coefficients10
2.4.2Huffman Coding of the DC Coefficients12
CHAPTER 3 SOPC DESIGN METHODOLOGY14
3.1 INTRODUCTION OF SOPC BUILDER DESIGN FLOW15
3.1.1 SOPC Design Flow and Features16
3.1.2 Definition and Customization17
3.1.3 Integration19
3.1.4 Software Generation20
3.1.5 System Verification20
3.2 NIOS EMBEDDED PROCESSOR DEVELOPMENT BOARD21
3.2.1 Development Board Features21
3.2.2 The Nios Development Tool Flow22
CHAPTER 4 A WEB-BASED SURVEILLANCE SYSTEM IMPLEMENTATION24
4.1 THE OVERALL ARCHITECTURE OF WEB-BASED SURVEILLANCE SYSTEM25
4.2 THE FIRST IMPLEMENTATION METHOD26
4.2.1 The 10/100 MAC IP Design26
4.3 THE SECOND IMPLEMENTATION METHOD35
4.4 ARCHITECTURE DESIGN OF IMAGE CAPTURE36
4.5 ARCHITECTURE DESIGN OF EMBEDDED WEB SERVER SYSTEM36
4.6 ARCHITECTURE DESIGN OF JPEG COMPRESSION39
4.6.1 The Nios processor establishment39
4.6.2 The JPEG compression by embedded processor41
4.6.3 The Experiment result of JPEG Compression on Nios43
CHAPTER 5 CONCLUSIONS AND FUTURE WORK46
REFERENCE48

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