(3.227.208.0) 您好!臺灣時間:2021/04/18 13:10
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳昭鈞
研究生(外文):Zhao-Jung Chen
論文名稱:適用於網路資訊家電之低成本系統晶片
論文名稱(外文):A Low-Cost SoC for Information Appliance Networking
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:91
語文別:中文
論文頁數:88
中文關鍵詞:系統週邊通訊協定系統晶片超高速乙太網路網路資訊家電
外文關鍵詞:Communication ProtocolSystem PeripheralSystem on a Chip10/100/1000Mbps Ethernet MACNetworking Infromation Appliance
相關次數:
  • 被引用被引用:0
  • 點閱點閱:105
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文中,我們將針對目前屬於家庭電器的產品,提出一套架構可適用於快速整合網路功能至原有的家電中,藉此有效地縮短資訊家電產品的開發成本與時程。同時針對乙太網路媒體存取介面,提供利用硬體進行加速TCP/IP總和檢查計算。主要的焦點在資訊家電系統的硬體與軟體開發流程,其中針對包括下一代區域網路Gigabit Ethernet介面,及利用硬體進行TCP/IP總和檢查機制的討論。
In this paper, we will provide an example of SoC for Information Appliance. We will use the SoC to reduce design-time and design-cost for IA products. Simultaneously, we will also enhance the Gigabit Ethernet Media- Access-Controller (MAC) with Hardware TCP/IP Checksum module. It can alleviate the CPU loads effectively, especially in longer length packets.
1. 論文簡介 1
1.1. 研究動機 1
1.2. 研究方法 3
1.3. 研究貢獻 5
2. 相關研究探討 6
2.1. Software based Network Architecture 6
2.2. Emerging ASICs based Network Architecture 7
2.3. Network Processor based Network Architecture 8
3. 客戶化硬體環境(Customized H/W Environment) 10
3.1. 微處理器(Microprocessor) 11
3.2. 網路硬體介面(Network H/W Interface) 14
3.2.1. 10/100/1000 Mbps Ethernet MAC 14
3.2.2. Ethernet MAC Soft IP Products’ Comparison 27
3.2.3. Ethernet Hardware TCP/IP Checksum Enhancement 28
3.3. 系統週邊(System Peripherals) 31
4. 客戶化軟體環境(Customized S/W Environment) 32
4.1. 系統韌體(System Firmware) 34
4.1.1. 中斷處理程式(Interrupt Handler) 34
4.1.2. 記憶體緩衝區管理(Memory Buffer Management) 35
4.2. 通訊協定(Communication Protocols) 39
4.2.1. 位址解析通訊協定(Address Resolution Protocol) 39
4.2.2. 網際網路通訊協定(Internet Protocol) 42
4.2.3. 使用者資料包通訊協定(User Datagram Protocol) 46
4.3. 應用程式(Applications) 49
4.3.1. 網路連線處理程式(Network Connection Handle Program) 49
4.3.2. 影像擷取程式(Image Capture Program) 53
5. 系統驗證(System Verification) 54
5.1. 子系統驗證(Subsystem Verification) 54
5.2. 系統整合性驗證(System Integration Verification) 59
5.2.1. Integrated System RTL Simulation Verification 59
5.2.2. Integrated System FPGA’s Demonstration 64
6. H/W Checksum對於系統效能之影響分析 67
6.1. 採用軟硬體執行總和檢查的差異 67
6.1.1. Software TCP/IP Checksum 67
6.1.2. Ethernet MAC H/W TCP/IP Checksum 68
6.2. 網路監視系統效能分析(Case Study) 70
6.2.1. 在32位元微處理器架構下採用16位元記憶體頻寬之影響 72
6.2.2. 使用乙太網路介面硬體加速機制之影響 74
7. 結論(Conclusion) 75
8. 未來工作(Future Work) 76
9. 參考文獻(Reference) 77
[1]Williams, J., “Architectures for Network Processing,”
VLSI Technology, Systems, and Applications, 2001.
[2]Paulin, P.G.; Karim, F.; Bromley, P., “Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools,” Design Automation and Test, Europe, 2001.
[3]“The Role of Network Processors in Next Generation Networks,” Intel Network Processor Division Corporation , August 2001
[4]“The Challenge for Next Generation Network Processors,” Agere Systems Proprietary, April 2001
[5]“Building Next Generation Network Processors,” Agere Systems Proprietary, April 2001
[6]Heer, D.N.; Maher, D.P., “The heart of the new information appliance,“ Consumer Electronics IEEE Transactions , Volume: 41 Issue: 3 , Aug. 1995
[7]Read, S., “Successful programming for information appliances,” Wescon/97. Conference Proceedings , 1997
[8]Shang-yi Chiang, “Foundries and the Dawn of an Open IP Era,” Computer , Volume: 34 Issue: 4 , April 2001
[9]Michael Keating and Pierre Bricaud, Reuse Methodology Manual For SYSTEM-ON-A-CHIP DESIGNS Second Edition, KLUWER ACADEMIC PUBLISHERS.0
[10]Thompson, G.O., “Work Progresses on Gigabit Ethernet,”
Computer , Volume: 30 Issue: 5 , May 1997
[11]Clark, D.,”Are ATM, Gigabit Ethernet Ready for Prime Time?,”
Computer , Volume: 31 Issue: 5 , May 1998
[12]Frazier, H.; Pesavento, G., “Ethernet Takes on the First Mile,”
IT Professional , Volume: 3 Issue: 4 , July-Aug. 2001
[13]Finkler, S.; Sidhu, D,. “PERFORMANCE ANALYSIS OF IEEE 802.3z GIGABIT ETHERNET STANDARD,”
Global Telecommunications Conference, 1999. GLOBECOM ''99 , Volume: 2 , 1999
[14]Ross, M.; Bechtolsheim, A.; Le, M.T.; O''Sullivan, J., “FX1000: a high performance single chip Gigabit Ethernet NIC,”
Compcon ''97. Proceedings, IEEE , 1997
[15]Frazier, H.; Johnson, H., “Gigabit Ethernet From 100 to 1,000 Mbps,”
IEEE Internet Computing , Volume: 3 Issue: 1 , Jan.-Feb. 1999
[16]IEEE Std 802.3, 2000 Edition
[17]JAYANT KADAMBI, IAN CRAYFORD, MOHAN KALKUNTE,
Gigabit Ethernet Migrating to High-Bandwidth LANs
[18]Jeremy Bentham, TCP/IP Learn Web Servers for Embedded Systems
[19]Kenneth J. Christensen, Mart Molle, Sifang Li, “Comparison of the Gigabit Ethernet Full-Duplex Repeater, CSMA/CD, and 1000/100-Mbps Switched Ethernet,”
Local Computer Networks, 1998. LCN ''98. Proceedings., 23rd Annual Conference on , 1998
[20]Young-Ho Cha, “An Embedded 16 bit Microprocessor,”
The second IEEE Asia Pacific Conference on ASIC, 2000
[21]AMBATM Specification (Rev 2.0)
[22]http://www.cic.edu.tw/
[23]http://www.opencores.org/
[24]http://www.mentor.com/
[25]http://www.cisco.com/
[26]http://www.arm.com/
[27]http://www.mltc.com.tw/
[28]Ming-Chih Chen; In-Jer Huang; Chung-Ho Chen, “Parameterized MAC unit implementation,” Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific , 2001
[29]教育部八十八學年度大學校院矽智產(SIP)設計競賽優等
[30]黃能富, 區域網路與高速網路
[31]W. Richard Stevens, TCP/IP Illustrated Volume1
[32]W. Richard Stevens, TCP/IP Illustrated Volume2
[33]http://www.samsung.com/
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔