臺灣博碩士論文加值系統

ARM的高效能、低耗電量與低成本等優點，是通訊、資訊家電及手持式裝置所需要的功能。根據Gartner的資料，在嵌入式微處理器市場中，ARM的市佔率最高，達54%，目前全球行動電話中，約有70％都是使用ARM核心技術。ARM之所以成功在於它擁有一些特別的硬體設計。本論文最主要的目的就是探討ARM這顆嵌入式微處理器的五種硬體特色在各種不同應用產品的實用性及對效能/成本的影響。而針對ARM的Banked Register這項硬體特色，我們自行設計暫存器自動備份/還原機制來取代之，這項設計除了能保持與原架構的相容性外，暫存器檔更進一步減少了27.6%的電路面積與減少了18.4%的暫存器讀取時間。對於測試機制所需用到的scan chain，在scan chain的選擇方式上我們以更簡單的方式（TAP指令）來達成

All of the communication, IA, and the cellular phone need the capabilities which can be provided by the ARM microprocessor that has the advantages with high efficient, low power consumption, and low cost. According to the market research that Gartner proposed, ARM occupied the highest with 54% at the market of embedded microprocessor, and 70% of the cellular phones utilize the ARM kernel techniques in the whole world. The success of ARM is determined by the different on the hardware design compared with the general embedded microprocessor. In my thesis, the significant propose is to study the practicability and the essentiality of the hardware characters of the ARM microprocessor applied on different products. We design “automatic register backup/restore system” to replace ARM’s banked registers. This design is capable of reducing the circuit area of the register file by 27.6% and reducing the read delay of register file by 18.4%. We use a simpler method (TAP instruction) to select scan-chain for test mechanism.

List of Figure III

List of Tables V

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 1
1.3 Research Approach and Flow 2
1.4 Contributions of This Thesis 3
1.5 Thesis Organization 3

Chapter 2 Thumb Instruction Set 4
2.1 Related Work 4
2.1.1 Code Size Problem 4
2.1.2 Multiple Instruction Sets 5
2.2 ARM/Thumb Code：Benchmark Analysis 8
2.3 Hardware Performance/Area Exploration 13
2.4 Conclusion Remark 16

Chapter 3 Banked Register 18
3.1 Related Work 18
3.1.1 Registers Organization for Exception Handling 18
3.1.2 SPARC：Register Windows 19
3.1.3 Banked Registers of ARM Microprocessor 20
3.1.4 Two Translation Modes 22
3.2 Exception Handling of ARM Microprocessor 23
3.3 Implementation Alternatives 27
3.3.1 Single Execution Mode 27
3.3.2 Automatic Register Backup/Restore Mechanism 29
3.3.2.1 Backup Register Organization 29
3.3.2.2 Backup Register Integration 31
3.3.2.3 Backup Register Operation 33
3.3.2.4 Register Backup and Restore in Exceptions 38
3.3.2.5 Exploration of Hardware Implementation 43
3.4 Automatic Register Backup/Restore System Verification 46
3.4.1 RTL Automatic Function Verification 47
3.4.2 FPGA Verification 48
3.5 Conclusion Remark 51


Chapter 4 64-bit Multiply-Accumulate Operation 52
4.1 Related Work 52
4.1.1 Dual Precision of Multiply-Accumulator 52
4.1.2 The ARM Multiply-Accumulate Instructions 53
4.2 Implementation Alternatives 57
4.2.1 Software Patch 59
4.3 Conclusion Remark 62

Chapter 5 Scan Chain Selection Approach 64
5.1 Related Work 64
5.1.1 IEEE Std. 1149.1 Boundary-Scan Architecture 64
5.1.2 Integrated Circuit Test Mechanism and Method of ARM
Microprocessor 65
5.2 Scan-Chain Selection Approach 68
5.3 Verification 69
5.4 Conclusion Remark 71

Chapter 6 Conditional Execution 72
6.1 Related Work 72
6.1.1 Branch Removal 72
6.1.2 Introduction to Conditional Instruction 72
6.2 Benchmark Analysis 77
6.3 Performance/Cost Exploration 80
6.4 Conclusion Remark 82

Chapter 7 Conclusions and Future Work 83

References 85

Appendix A Benchmarks 87

[1].Gartner Inc. http://www3.gartner.com/Init
[2].M. Keating and P. Bricaud, "Reuse Methodology Manual for System-on-a-Chip Designs,2nd Edition," Kluwer Academic Publishers, 1999.
[3].Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge, "Improving Code Density Using Compression Technique," Proceedings of the 30th Annual International Symposium on
Microarchitecture, Dec. 1997, pp.194-203
[4].I. Kadayif, M.T. Kandemir, "Instruction compression and encoding for low-power systems," 15th Annual IEEE International ASIC/SOC Conference, pp.301-305, 2002.
[5].L. Benini, A. Macii, E. Macii, and M. Poncino, "Selective instruction compression for memory energy reduction in embedded systems," In Proc. International Symposium on Low Power Electronics and Design, August 1999.
[6].Simon Segars, "Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications," IEEE Proceedings of COMPCON, pp.176-181, 1996.
[7].David V. Jagger, C. Hinton, "Multiple Instruction Set Mapping," Advanced RISC Machines Ltd., U.S. Patent 5568646, 1996. http://www.uspto.gov/patft/index.html
[8].D. V. Jagger, C. Hinton, "Data Processing with Multiple Instruction Sets," Advanced RISC Machines Ltd., U.S. Patent 5740461, 1998. http://www.uspto.gov/patft/index.html
[9].E. C. Nevill, "Interoperability with Multiple Instruction Sets," Advanced RISC Machines Ltd., U.S. Patent 5758115, 1998. http://www.uspto.gov/patft/index.html
[10].E. C. Nevill, "Interoperability with Multiple Instruction Sets", Advanced RISC Machines Ltd., U.S. Patent 6021265, 2000. http://www.uspto.gov/patft/index.html
[11].K. Kissell, "MIPS16: High-density MIPS for the Embedded Market", Technical report, Silicon Graphics MIPS Group, 1997.
[12].MIPS32TM Architecture for Programmers Volume IV-a: The MIPS16e? Application-Specific Extension to the MIPS32? Architecture, MIPS Technologies Inc., 2002.
[13]."Writing Efficient C for ARM," Application Note 34, Advanced RISC Machines Ltd., 1998.
[14].MIPS32 4KTM Processor Core Family Software User''s Manual, MIPS Technologies Inc., 2002.
[15].PPC440 CPU Core User''s Manual, IBM Corporation, 2002.
[16].W. Joy, P. Alto, Robert B. Garner, S. Jose, "RISC processing unit which selectively isolates register windows by indicating usage of adjacent register windows in status register," Sun Microsystems, U.S. Patent 5159680, 1992. http://www.uspto.gov/patft/index.html
[17].David V. Jagger, "Exception Handling Method and Apparatus in Data Processing Systems," Advanced RISC Machines Ltd., U.S. Patent 5701493, 1997, http://www.uspto.gov/patft/index.html
[18].Alasdair R.P. Thomas, "Register Substitution during Exception Processing," Advanced RISC Machines Ltd., U.S. Patent 5386563, 1995. http://www.uspto.gov/patft/index.html
[19].梁景哲, "選擇存取暫存器之方法", 智原科技股份有限公司, 中華民國專利 494644, 2002.
[20].The SPARC Architecture Manual Version 8, SPARC International Inc., 1992.
[21].Hitachi SuperH? RISC Engine SH-1/SH-2/SH-DSP Programming Manual, Hitachi Ltd., 1999.
[22].ARM7TDMI Data Sheet, Advanced RISC Machines Ltd., 1995.
[23].David J. Seal, G.. Larri, "Data Processing Using Multiply-Accumulate Instructions," Advanced RISC Machines Ltd., U.S. Patent 5583804, 1996. http://www.uspto.gov/patft/index.html
[24].ARM Software Development Toolkit User Guide, Advanced RISC Machines Ltd., 1997.
[25].IAR Systems Software Inc. http://www.iar.com
[26].IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1.1a, 1993.
[27].Simon A. Segars, "Integrated Circuit Test Mechanism and Method," Advanced RISC Machines Ltd., U.S. Patent 5636227, 1997. http://www.uspto.gov/patft/index.html
[28].Randal E. Bryant, "Alpha Assembly Language Guide," Carnegie Mellon University,
http://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/ 15347-s98/public/doc/alpha-guide.pdf
[29].Ken Monk, "Inside IA-64," http://www.mis.coventry.ac.uk/~kenmk/203cs/ia64-6.html
[30].Jonathan P. Vogel, Bruce K. Holmer, "Analysis of the conditional skip instructions of the HP precision architecture," Proceedings of the annual international symposium on Microarchitecture, November 1994.
[31].J. Huck, D. Morris, J. Ross, A. Knies, H. Mulder, and R. Zahir," Introducing the IA-64
architecture," IEEE Micro, Volume: 20 Issue: 5, Sep/Oct 2000.
[32].C. Dulong, "The IA-64 architecture at work," Computer, Volume: 31 Issue: 7, Jul 1998, Page(s): 24-32.
[33].TM-1300 Media Processor Data Book, Philips Semiconductor, 2000.
[34].TMS320C6000 CPU and Instruction Set Reference Guide, Texas Instruments Incorporated, October 2000.
[35].M. Evers, Tse-Yu Yeh, "Understanding branches and designing branch predictors for high-performance microprocessors," Proceedings of the IEEE, Volume: 89 Issue: 11, Nov. 2001, Page(s): 1610 -1620
[36].AS950 ARM Applications Library Programmer''s Guide, Advanced RISC Machines Ltd., 1999.
[37]."New ARM Thumb-2 Core Technology Provides Industry-Leading Levels of Code Density And performance," Press Releases, June 2003. http://www.arm.com/news/PrimeXsysPR
[38].J.V. Woods, P. Day, S.B. Furber, J.D.Garside, N.C. Paver, S. Temple, "AMULET1: an asynchronous ARM microprocessor," IEEE Transactions on Computers, Volume: 46 Issue: 4 ,April 1997 , Page(s): 385 -398
[39].賴奇劭, "ARM7微處理器之衍生架構," 碩士論文, 國立中山大學資訊工程學系, 2001.
[40].An Introduction to Thumb?, Advanced RISC Machines Ltd., 1995.
[41].丁邦安, "嵌入式微處理器核芯應用系列(二)ARM核芯簡介," IC Design, February 2001, pp.38-56
[42].M. Morris Mano, Charles R. Kime, "Logic and Computer Design Fundamental 2/e Updated," Prentice Hall, 2000.