(3.230.143.40) 您好!臺灣時間:2021/04/23 16:00
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:蘇郁文
研究生(外文):Yu-Wen Shu
論文名稱:在記憶體處理器系統上以串列為基礎的低耗能排程機制
論文名稱(外文):A List-based Low Power Scheduling Mechanism for Processor-in-Memory Systems
指導教授:黃宗傳
指導教授(外文):Tsung-Chuan Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:50
中文關鍵詞:記憶體處理器耗能-延遲時間乘積串列排程
外文關鍵詞:energy-delay productlist schedulingProcessor-in-Memory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:78
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
在電腦系統的設計上能量之消耗逐漸成為重要的課題。截至目前大部份低耗能的研究都著重在硬體架構及半導體元件之設計上,而較少人運用軟體最佳化的技術。在這篇論文中,我們將串列排程(list scheduling)技術應用在記憶體處理器(Processor-in-Memory)系統上,以減少其耗能但不犧牲程式的執行效能。在以串列排程為基礎的低耗能排程中,每個可以被排程的區塊將會先存放到優先串列(priority list)中,而排程的核心則是利用移動性權重的概念來決定那一個區塊可以被優先排程。工作在分配給處理器時則是依據「耗能-延遲時間乘積」來做為能量成本的模型。最後我們提出實驗之結果並加以討論。
Power consumption is gradually becoming an important issue in designing computing systems. Most of the low power researches focused on semiconductor technique and hardware architecture design but less utilized the techniques of software optimization. In this thesis, list scheduling is employed to reduce the energy cost for the Processor-in-Memory system not at the sacrifice of execution performance. In our list-based low power scheduling algorithm, a priority list will be maintained for each scheduling step. The scheduling kernel utilizes the priority of mobility to determine which task will be scheduled to the suitable processor based on the energy cost model of energy-delay product. The experimental results are presented and discussed.
中文摘要…………………………………………………I
英文摘要…………………………………………………II
目錄………………………………………………………III
圖目錄……………………………………………………V
表格目錄…………………………………………………VIII
第一章 簡介………………………………………………1
第二章 相關研究…………………………………………4
第三章 PIM架構和SAGE系統介紹……………………12
第3.1節 PIM的架構描述…………………………………12
第3.2節 SAGE系統介紹…………………………………15
第3.2.1節 陳述分割模組…………………………………16
第3.2.2節 超區塊圖建立模組……………………………16
第3.2.3節 權值評估機制和1H-nM排程機制……………17
第四章 低耗能之工作排程………………………………19
第4.1節 成本模式………………………………………19
第4.2節 以串列為基礎的低耗能排程機制……………22
第4.2.1節 定義……………………………………………22
第4.2.2節 Execution_Order和Mobility函數之說明………24
第4.2.3節 Insert_Ready函數之說明………………………25
第4.2.4節 Distribution函數之說明…………………………26
第4.2.5節 Load_Balance函數之說明………………………27
第4.2.6節 Fill_Interval函數之說明…………………………31
第4.2.7節 Check_List函數之說明…………………………33
第五章 範例…………………………………………………35
第六章 實驗結果……………………………………………42
第七章 結論…………………………………………………47
參考文獻……………………………………………………48
[1]A. Chandrakasan et al., "Optimizing Power Using Transformations," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 14 no. 1, pp. 12-31, 1995.
[2]A. Parikh, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, "Energy-Aware Instruction Scheduling," In: Proc. Of 7th International Conference on High Performance Computing-HiPC 2000, pp. 335-344, December, 2000.
[3]Anand Raghunathan, Niraj K. Jha and Sujit Dey, "HIGH-LEVEL POWER ANALYSIS AND OPTIMIZATION," Kluwer Academic Publishers, 1998.
[4]B. W. Suessmith and G. P. II, "PowerPC 603 Microprocessor Power Management," Commun. ACM, vol. 37, no. 6, pp. 43-46, 1994.
[5]Centrino overview. http://developer.intel.com/
[6]Dah-Lih Jeng and Liang-Chuan Hsu "Improving Register Relabeling Technique to Reduce Power Consumption of Pipelined Datapath for RISC Machines," In Proc. of The Eighth Workshop on Compiler Techniques for High-Performance Computing, 2002.
[7]Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin, "HIGH-LEVEL SYNTHESIS: Introduction to Chip and System Design," Kluwer Academic Publishers, 1992.
[8]F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. DeMan, "Global Communication and Memory Optimizing Transformations for Low power Signal Processing Systems," In Proc, IEEE Workshop on VLSI Signal Processing, pp. 178-187, 1994.
[9]H. J. Jean, "Designing New Scheduling Mechanisms for Processor-in-Memory Systems," Master Thesis, Department of Electrical Engineering, National Sun Yat-Sen University, 2001.
[10]Mark Horowitz, Thomas Indermaur and Ricardo Gonzalez, "Low-Power Digital Design," IEEE International Symposium on Low Power Electronics, pp. 8-11, October, 1994.
[11]Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, "A Framework for Dynamic Energy Efficiency and Temperature Management". In Proc. of 33rd International Symposium on Microarchitecture, December, 2000.
[12]M. Y. Chen, "The Implementation of Task Evaluation and Scheduling Mechanisms for Processor-in-Memory Systems," Master Thesis, Department of Electrical Engineering, National Sun Yat-Sen University, 2002.
[13]Ricardo Gonzalez and Mark Horowitz, "Energy Dissipation in General Purpose Processors," IEEE International Symposium on Low Power Electronics, October, 1995.
[14]Veenstra, and R. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," in Proc. International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, pp. 201-207, 1994.
[15]S. L. Chu, T. C. Huang, and L. C. Lee, "Improving workload balance and code optimization in processor-in-memory systems," in Proc. 8th International Conference on Parallel and Distributed Systems, pp. 273-278, 2001.
[16]S. L. Chu, "SAGE: An Automatic Analyzing and Parallelizing System to Improve Performance and Reduce Energy on a New High-Performance SoC Architecture-Processor-in-Memory," Ph.D. Thesis, Department of Electrical Engineering, National Sun Yat-Sen University, 2002.
[17]Steven S. Muchnick, "Advanced Compiler Design and Implementation," Morgan Kaufmann Publishers, 1997.
[18]T. C. Huang, and S. L. Chu, "SAGE: A New Analysis and Optimization System for FlexRAM Architecture," in Proc. 2nd Workshop on Intelligent Memory Systems, 2000.
[19]T. C. Huang, and S. L. Chu, "A New Analysis Approach for Intelligent Memory Systems," in Proc. ISCA 16th International Conference on Computers and Their Applications, pp. 452-457, 2001.
[20]Tiwari, V., Malik, S., Wolfe, A. "Compilation Techniques for low energy: an overview," In 1994 Digest of Technical Papers, IEEE Symposium on Low Power Electronics, pp. 38-39, 1994.
[21]V. Tiwari, S. Malik, A. Wolfe, and M.T.-C. Lee, "Instruction Level Power Analysis and Optimization of Software," J. VLSI Signal Process. vol. 13, nos. 2/3, pp. 223-228, 1996.
[22]W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, "Numerical Recipes in Fortran 77," Cambridge University Press, 1992.
[23]Y. B. Liu, "The Design of a New Program Decomposition Mechanism for Processor-in-Memory Systems," Master Thesis, Department of Electrical Engineering, National Sun Yat-Sen University, 2002.
[24]Y. Kang, W. Huang, S. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, "FlexRAM: Toward an Advanced Intelligent Memory System," International Conference on Computer Design, 1999.
[25]Yi-Ping, Chingren Lee and Jenq Kuen Lee "Compiler Optimization for Low Power on Power Gating," In Proc. of The Eighth Workshop on Compiler Techniques for High-Performance Computing, 2002.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔