臺灣博碩士論文加值系統

隨電子產品輕薄短小及功能多樣化之潮流，傳統之電子封裝型態已無法符合新世代產品於體積或功能之要求，故發展不同型態之封裝體已呈必然之趨勢。而目前封裝設計者主要以晶圓級封裝（Wafer Level Package；WLP）及晶片尺寸級封裝（Chip Scale Package；CSP）技術為基礎，以發展出新式之封裝技術，達到封裝體性能及可靠度之要求。
而本論文亦提出一新式之晶圓/晶片尺寸級封裝體（WL-CSP），利用位於晶片與印刷電路板間之應力緩衝層及發泡式基板，提高晶片與印刷電路板之間距，以舒緩晶片與印刷電路板間不匹配之熱膨脹量。此一構想可將晶片與印刷電路板間不匹配之熱膨脹量，平均分佈至更大的區域以提高銲錫接點之壽命，如此將可有效解決具有較大晶片尺寸之晶圓級封裝體可靠度不佳的問題。
而為清楚瞭解所提出之新式封裝結構可靠度與發泡基板及應力緩衝層之關係，本論文利用有限元素分析軟體ANSYSâ與三維有限元素模型，對此新式封裝結構之重要參數如：應力緩衝層厚度、不同型態發泡基板之厚度、彎曲角度及高度進行模擬與分析，並深入探討其結構參數與封裝體可靠度之關係。
而分析結果指出此新式封裝體之發泡基板及應力緩衝層結構，的確可舒緩錫球所承受之熱應力，進而達到提高錫球熱疲勞壽命之目的。然根據ANSYSâ之模擬結果可發現各項結構參數與錫球之熱疲勞壽命，實具有不同程度之關係及趨勢。此外本論文亦探討發泡式基板與應力緩衝層間之剝離問題，以及銅導線架於熱循環負載所承受之應力。最後期許本論文研究之結果可作為日後相關封裝結構設計參考之依據。

With the trend of multi-function and minimizing volume, original electronic package type has not met the performance of new-generation product. Consequently, new type packages based on WLP and CSP skills are developed to achieve the demand of reliability.
New WL-CSP with stress buffer layer and bubble-like plate are proposed to improve the solder joint fatigue life. Therefore the thermal stress caused by CTE mismatch could be reduce. Finally, the reliability of the WLP with larger die size could be enhanced by this new design.
In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYSâ is utilized. The design parameters include the thickness of stress buffer layer, thickness, bending angle and height of different type bubble-like plate.
It could be found in the FEM analysis results that the stress buffer layer and bubble-like plate can not only relax the thermal stress of solder joints but also achieve the goal of enhancing package reliability. However, the relationship between each parameter and solder joint fatigue life has a dissimilar trend. Finally, the peeling stress between stress buffer layer as well as two different type bubble-like plate is discussed and the stress state of leadframe is also analyzed in the research.

目 錄
頁次
第一章 緒論 …………………………………………………… 1
1.1電子封裝簡介………………………………………………… 1
1.1.1晶圓/晶片尺寸級封裝（WL-CSP）……………………. 1
1.1.2電子封裝可靠度與加速度測試………………………. 4
1.1.2.1電子封裝可靠度測試……………………………. 5
1.1.2.2加速度測試………………………………………. 6
1.2研究動機……………………………….…………………….. 7
1.3文獻回顧…………………………………….……………….. 8
1.4研究目標…………………………….……………………….. 12
第二章 理論基礎……………………………………………….. 13
2.1錫球幾何外型預測…………………………………………… 13
2.1.1力平衡觀念之解析法……………………………………. 13
2.1.2能量法（Energy-Based Method）………………………. 17
2.2非線性理論…………………………………………………… 20
2.2.1 Newton-Raphson法……………………………………… 21
2.2.2降伏準則（Yield Criterion）…………………………. 23
2.2.3硬化準則（Hardening Rule）…………………….…….. 25
2.3可靠度估算準則（Reliability Criterion）……………… 26
第三章 研究方法…………………………………………….. 29
3.1實驗之驗證（128 MB DRAM之加速熱循環試驗結果）.….. 29
3.1.1有限元素模型之建立……………………………………. 30
3.1.2模擬結果與實驗之驗證………………………………….. 31
3.2發泡式基板封裝體有限元素模型之建立……………….… 33
3.2.1有限元素模型之幾何尺寸及邊界條件的設定…………. 34
3.2.2有限元素模型之材料參數設定…………………………. 35
3.2.3有限元素模型之負載…………………………………… 36
3.3有限元素模型之參數化分析………………………………… 36
3.3.1基準有限元素模型………………………………………. 37
3.3.1.1中空圓柱式發泡基板之基準有限元素模型……….. 37
3.3.1.2浪板式發泡基板之基準有限元素模型……………... 38
3.3.2 幾何參數化分析之有限元素模型……………………… 38
3.3.2.1發泡基板彎曲角度參數化之有限元素模型……….. 38
3.3.2.2發泡基板彎曲高度參數化之有限單元模型……….. 39
3.3.2.3發泡基板厚度參數化之有限單元模型……….……. 39
3.3.2.4應力緩衝層厚度之參數化有限元素模型………….. 40
第四章 分析結果與討論…………………….…………………. 41
4.1參數化分析之銲錫接點加速熱循環試驗模擬結果………… 41
4.1.1基準有限元素模型之模擬結果…………………………. 41
4.1.1.1中空圓柱式發泡基板之模擬結果………………….. 41
4.1.1.2浪板式發泡基板之模擬結果………………………... 43
4.1.1.3兩發泡式基板之結構勁度比較……………………... 43
4.1.2有限元素模型之幾何參數化分析模擬結果……………. 44
4.1.2.1發泡基板彎曲角度之參數化模型模擬結果………... 44
4.1.2.2發泡基板彎曲高度之參數化模型模擬結果……….. 46
4.1.2.3發泡基板厚度之參數化模型模擬結果…………….. 47
4.1.2.4應力緩衝層厚之度參數化模型模擬結果…………... 48
4.1.3參數化分析之綜合比較………………………………….. 49
4.2發泡基板與應力緩衝層間之剝離應力………………………. 50
4.3銅導線架及晶片之應力狀態…………………………………. 52
第五章 結論與未來展望……….………………………………. 54
參考文獻 ………………………………………………………… 57
圖表……….………………………………………………………. 63

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