電晶體寬度調整是最佳化時間的方法之一，我們利用一個非線性的程式方法和SPICE資料萃取延遲模型來解此問題。實驗結果顯示SPICE資料萃取延遲模型比簡單的RC延遲模型和Elmore延遲模型準確。我們在此論文中所提出的方法，調整每一個電晶體最多兩次，這是比其他論文，例如曲線程式方法要好。由於不同的電路，電路特性會有很大的不同，在成本函數中的參數可以被調整以符合電路的特性。
電晶體寬度調整是最佳化時間的方法之一，增加或減少電晶體寬度可以影響電路的延遲時間。電晶體寬度調整問題的目標為在滿足電路延遲時間限制下，使得電晶體的面積越小越好。
最近幾年，有許多的方法來解電晶體寬度調整問題包含有，啟發式方法，曲線程式方法，非線性程式方法等，有於電晶體寬度調整問題的解集合很大，啟發式方法缺乏整體電路的概念，曲線程式方法執行時間太長。
這些方法大多採用理論的延遲模型例如簡單的RC延遲模型，Elmore延遲模型，但是不同的電路電路特性會有很大的不同，有許多的因素影響電路的行為表現例如負載電容，在此篇論文中，延遲模型是由SPICE電路模擬得到，我們可以從SPICE電路模擬結果中得到兩種資訊，第一，延遲關係式，第二，相關的參數。
我們利用一個非線性程式方法[2] 來解電晶體寬度調整問題，在演算法中Slack的概念被考慮，演算法的流程見圖Fig. 1-3。在關鍵路徑分析階段，電路被轉換成多級的圖形，並給定初始的電晶體寬度，我們計算每一邏輯閘的延遲，且利用深度優先搜尋法決定關鍵路徑。在電晶體寬度調整階段，演算法利用延遲關係式來從輸出到輸入來調整電晶體，幾乎最佳化的電晶體寬度可以得到，在電晶體寬度微調整階段，Slack的概念被用來估計某一電晶體寬度是否足夠，演算法從輸入到輸出來微調整電晶體滿足電路延遲時間限制下，使得電晶體的面積越小越好。
我們用SPICE電路模擬器套用數個電路來驗證延遲模型的準確性，實驗結果顯示，SPICE資料萃取延遲模型比理論延遲模型要準確，我們提出的方法宇SPICE 電路模擬器的誤差在10%以下。

Transistor sizing is a timing optimization technique. We solve the transistor sizing problem by using a non-linear programming method with the SPICE Data Extracted Delay Model. The experiment result shows that the SPICE data extracted delay model is more precise than a simple RC or the Elmore delay model. The approach we proposed in this paper sized each transistor in the circuit twice at most. It is better than other approaches, such as convex programming and simulated annealing. It is because that the circuit characteristics of different circuits are much different. The parameters of the cost function could be modified in order to meet the circuit characteristics.

Abstract ………………………………………………………………i
Contents………………………………………………………………ii
List of Figures……………………………………………………iii
List of Tables………………………………………………………iv
Chapter 1 Introduction ……………………………………………1
Chapter 2 Related Work ……………………………………………5
Chapter 3 Models ……………………………………………………7
3.1 The Related Parameter ……………………………………8
3.2 The Delay Model ……………………………………………9
3.3 Transistor Sizing Cost Function………………………11
3.4 Transistor Desizing Cost Function……………………12
Chapter 4 Algorithms………………………………………………14
4.1 Critical Path Analysis …………………………………14
4.2 Transistor Sizing…………………………………………16
4.3 Transistor Desizing………………………………………18
Chapter 5 Experimental Results…………………………………22
Chapter 6 Conclusions… …………………………………………27
References……………………………………………………………28

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