臺灣博碩士論文加值系統

通常在設計一份超大型積體電路時，到了設計流程的後面步驟，可能由於設計上的錯誤，時序、面積、功率達不到預期的目標，或者設計的規格有了些許的變動，以致於我們得重新去修改目前或舊有的電路設計以修正設計上的錯誤或符合新的要求，而我們就稱這個過程叫做工程變動 (ECO)。由於製程上愈來愈先進，光罩的花費在設計的成本上所佔有的比例也愈來愈高，因此目前很多工程變動的方法把重心都放在節省光罩的成本上。而傳統的工程變動的方法是在原有的電路設計上隨意的放置一些冗餘的邏輯閘，一旦有工程變動的需求時，就利用這些冗餘的邏輯閘來達到工程變動的要求，雖然這樣的作法不用重新製作一整套的光罩，但是通常仍然需要改到多層的光罩。在這篇論文裡，我們提出了一個新的且結構較有組織的工程變動方法，我們的基本想法就是在一個電路設計裡放置一個可程式化的修正模組，而我們只要適當的程式化這個修正模組，就能達到工程變動的要求，最重要的一點是這個修正模組可以是只要修改一層光罩而達到修正效果的可程化邏輯陣列 (PLA )或唯讀性的記憶體 (ROM)，或者是不需要修改任何光罩的內嵌式FPGA，如此一來，我們不僅能節省重新設計整個電路所需的時間，更可以大大的節省光罩上的成本。另外我們提出了加入假的輸入 (pseudo inputs) 和假的輸出 (pseudo outputs)，來大大的降低可程式化修正模組可能造成的面積代價。而我們的實驗結果是另人感到激勵的。

In the later stage of a VLSI design, it is quite often to modify a design implementation to accommodate a new specification, design errors, or to meet design constraints. In addition to meeting the design schedule for the new implementation, the reduction of the mask set has become very critical. In this thesis, we propose a new method which adds a programmable rectification module on a design to reduce the mask cost and to improve the turn around time. When a modification is necessary, one can program the rectification module to achieve the new implementation. The rectification module can be designed by one-mask programmable gate array, or an embedded FPGA. To reduce the size needed for the rectification module, we also propose algorithms which can intelligently select some internal signals of the old implementation as pseudo primary inputs and primary outputs. Our experimental results are very encouraging.

Contents
Abstract 1
1. Introduction 2
2. Previous Work on Engineering Change 5
3. The Rectification Module 6
4. Algorithms for Choosing Proper Internal Nodes as Inputs/Outputs 10
5. Algorithms for Finding the Rectification Logic 13
6. Design Consideration for Input/Output Select Logic and One Mask Programmable Design Style 18
7. Engineering Change on Sequential Cells 21
8. Experimental Results 23
9. Conclusions 29
References 30

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