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研究生:胡琦偉
研究生(外文):Chi-Wei Hu
論文名稱:輸出導向電路分割之低功率設計
論文名稱(外文):Output-Pattern Directed Decomposition for Low Power Design
指導教授:黃婷婷黃婷婷引用關係
指導教授(外文):TingTing Hwang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:35
中文關鍵詞:低功率分割輸出導向
外文關鍵詞:low powerDecompositionoutput-pattern directed
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近年來,電路設計者必須把功率消耗的問題與面積跟工作的速度放在相同地位來考慮。這是因為晶片的面積越來越大,同時密度也越來越高。還有因為個人運算裝置與無線通訊的成長。在這些應用中,功率消耗的問題可能會是最嚴重的考量。另外也可能影響了晶片的可靠性。因為消耗高功率的晶片通常都很熱,而熱會造成晶片功能的錯誤。還有也會影響晶片的封裝與散熱,這些都有可能增加製造晶片的成本。
在本篇論文中,我們提出一個輸出導向的電路分割來減少功率消耗。我們觀察到一個現象,就是在某些電路中,在所有的輸出樣式(output pattern)中,並不是所有的輸出樣式都常常出現,而最常出現的輸出樣式只有幾種而已。根據這項觀察,我們提出了一個分割電路的架構還有演算法來產生這個分割電路。在我們的分割架構中,一個較小的部分是用來計算出一些很常出現的輸出樣式,而另一個較大的部分是用來計算其他不常出現的輸出樣式。因此大部分的時間只有較小的那個部分在動作,如此便可以節省功率的消耗。此外,我們提出了一個以有序二元決定圖表(OBDD)為基礎的啟發式演算法(heuristic algorithm)來計算輸出樣式的出現次數,這個演算法可以再很短的時間內得到結果。最後我們是拿一些MCNC的測試電路來展示我們的效果。從結果中可以知道,與原來的電路相比,我們的的分割演算法可以減少64.9%的功率消耗,同時只稍微增加了一些面積。

In this thesis, we present an output-pattern directed circuit decomposition to reduce power consumption. We observed that in some circuits, highly active output-pattern falls into only a few patterns.Based on this observation, we propose a decomposition architecture and an algorithm to synthesize the decomposed logic. In the decomposed architecture, one small part is used to compute a few highly occurred output-patterns, and the other large part is used for all the other infrequently occurred output-patterns. Consequently, most of time, only the small part of the circuit is active so as to reduce power consumption. In addition, we propose to use an OBDD-based heuristic algorithm to compute the output-pattern frequency in a very short CPU time. Several MCNC benchmark circuits were tested to show the performance. The results shows that the proposed method can achieve 64.9% reduction in power with little area increase as compared to circuits without decomposition.

1 Introduction 1
2 Decomposition Architecture Based on
Output-PatternDistribution 5
3 Output-pattern Directed Decomposition 13
3.1 OBDD-Based Output-Pattern Directed Partitioning of
Input-Pattern 13
3.2 ENC Simplification 17
4 Experimental Results 22
5 Conclusions 28

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[7] Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, and Xian-Jun Huang, "A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits," Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, pp. 84-90, Nov. 1999.
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[11] E. Sentovich et al., "SIS: A System for Sequential Circuit synthesis," Technology Report UCB/ERL M92/41, ERL, Department of EECS, University of California, Berkeley, May 1992.

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