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研究生:黃向陽
研究生(外文):Shiang-Yang Huang
論文名稱:H.264/AVC全搜尋可變大小區塊比對之硬體架構設計
論文名稱(外文):VLSI Architectures for Full-Search Variable-Size Block Matching in H.264/AVC
指導教授:王家祥
指導教授(外文):Jia-Shung Wang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:50
中文關鍵詞:全搜尋可變大小區塊比對
外文關鍵詞:Full-SearchVariable-SizeBlock Matching
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全搜尋移動向量估計(Full Search Motion Estimation)在視訊壓縮上是一項關鍵要素,目的是為了消除連續畫面在時間上的重複性。然而需要花費極高的計算量,因此無法直接滿足及時壓縮的需求。在過去提出了許多加速方法,除了採用一些快速搜尋演算法,另外則是仰賴特定的硬體實作。
H.264/AVC 是 ITU-T VCEG 所提出的最新視訊壓縮標準,在移動補償方面比先前的標準更具有彈性且富有效率。對於移動向量估計,H.264/AVC 標準提出一項新的特色:在大小為 16x16 的編碼區塊(Macroblock)內支援複合的區塊大小組合(16x16, 8x8 和 4x4)。這表示和先前的做法相比會產生更多的移動估計,因此當前的研究課題是如何設計出更有效率的硬體架構。
常見的硬體架構可分為三類:一維陣列、二維陣列以及樹狀結構。在本文中,針對 H.264/AVC 可變區塊大小移動向量估計,提出了有效的硬體架構。此外對於節省計算量來減少電力的消耗,可調適計算量(Computation-Aware)技巧也一併提出。

Full-search motion estimation is a key component on video compression to efficiently remove temporal redundancy between successive frames, however it spends huge amount of computations thus it is unlikely to satisfy the real time requirement directly. Several speed up approaches have been proposed, either adopt some fast search algorithms or rely on specific hardware implementations.
H.264/AVC is the latest video standard proposed by ITU-T VCEG, which is more flexible and efficient on motion compensation than those found in earlier standards. One new feature introduced by H.264/AVC standard about motion estimation is to support multiple possible block sizes (16x16, 8x8 and 4x4) for motion estimation within a macroblock of size 16x16. This indicates that much larger numbers of motion estimation would be produced than before, thus better effective hardware designs should be investigated nowadays.
Conventional hardware architectures can be categorized as three classes: one-dimensional array, two-dimensional array and tree architecture. In this thesis, several effective hardware architectures for fulfilling H.264/AVC variable block size motion estimation are proposed. Besides, computation-aware techniques for computation saving as well as power consumption are considered also.

Table of Contents iv
List of Figures v
List of Tables vi
Chapter 1 Introduction 1
1.1 Block-Based Hybrid Video Coding 2
1.2 Block-Based Motion Estimation 3
1.3 Thesis Organization 5
Chapter 2 Motion Estimation in H.264/AVC 6
2.1 Macroblock Partition in H.264/AVC 7
2.2 Bit Allocation of Motion Vectors 8
2.3 Universal Variable Length Coding 9
Chapter 3 Architectures for Block-based Motion Estimation 11
3.1 Levels of Memory Reuse 11
3.2 One Dimensional Systolic Array Designs 13
3.3 Two Dimensional Systolic Array Designs 16
3.4 Tree Architecture 18
Chapter 4 Proposed Architectures for H.264/AVC Motion Estimation 20
4.1 Elementary Units 20
4.2 On-Chip Memory 22
4.3 SAD calculation Stage 24
4.4 Merge Stage 27
4.4 Comparator Module 28
4.5.1 Rate-Distortion Cost Function 29
Chapter 5 Computation-Aware Design 32
5.1 Motion Vector Distribution Analysis 32
5.2 Analysis on Variable Size Blocks 33
5.3 Computation-Aware Architecture Design 35
Chapter 6 Experimental Results 38
Chapter 7 Conclusions 40
References 41

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[2] Information Technology─Generic Coding of Moving Pictures and Associated Audio Information: Video, ISO/IEC 13 818-2 (MPEG-2 Video), 2000.
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