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研究生:蔡志昇
研究生(外文):Steven
論文名稱:動態可程式化邏輯陣列之低功率設計
論文名稱(外文):Power Minimization for Dynamic PLAs
指導教授:張世杰張世杰引用關係
指導教授(外文):Shih-Chieh Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:39
中文關鍵詞:動態可程式化邏輯陣列低功率新架構超級乘積項降低切換機率
外文關鍵詞:dynamic PLAlow powernovel architecturesuper product termlowing switching activity
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在現今講求高效能的晶片設計當中,動態可程式化邏輯陣列因為具有速度快以及架構嚴謹有規律的特性,在一些控制邏輯設計中我們常可以看到他的應用,而為了講求高效能,通常都是利用NOR-NOR架構來設計,但卻也因此使得乘積線的切換機率(放電機率)大大的提高而造成功率的消耗。在本篇論文中,我們提出了一個新動態可程式化邏輯陣列的架構是利用合成超級乘積項來減少功率的消耗,而超級乘積項就是利用在NOR的架構上用NAND來合併兩條乘積線,進而使得切換機率降低。因為在合成超級乘積項可以有很多的配對選擇,因此我們還提供了一套完整的選取流程,利用最大加權配對的演算法來求得節省功率的最佳解。我們對110多個的MCNC測試檔做實驗,實驗的結果證明我們不只可以節省大部分的功率消耗也使得速度變得較快,平均來說功率消耗可以省大約32.1%,但時間也比傳統的架構快16%.

Dynamic PLAs which are built of the NOR-NOR structure have been very popular in high performance design because of their high speed and predictable routing delay. However, the NOR-NOR structure incurs high switching activity in product lines and thus results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the NAND functionality on top of the NOR structure, thus lowering the switching activities in the product lines as well as power consumption. Since there are many candidates for the super product lines, we have developed a CAD algorithm based on the maximum weighted matching to find optimal solution. In addition, the line reordering method is applied to further reduce the power consumption. We have performed experiments on a large set of MCNC benchmark circuits. Our experimental results not only show significant reduction in power but also the delay. On the average, the power consumption can be saved 54.86% and the delay can be improved 17.12%.

Contents
Abstract 2
Contents 3
List of Figures 4
List of Tables 5
Chapter 1 Introduction 6
Chapter 2 Power and Delay Computation in a Dynamic PLA 13
Chapter 3 A Novel Dynamic PLA Structure with Low Switching Activity 16
Chapter 4 Power Minimization by Using Maximum Weighted Matching 24
4.1 Non-Delay Constrained Power Minimization 24
4.2 Delay Constrained Power minimization 27
Chapter 5 Reordering Lines to Reduce the Power Consumption 29
Chapter 6 Experimental Results 33
Chapter 7 Conclusions 37
Reference 38

Reference
[1] G. M. Blair, “PLA design for single-clock,” IEEE J. Solid-State Circuits, vol. 27, pp. 1211-1213, Aug. 1992.
[2] R. K. Brayton et al., Logic minimization algorithms for VLSI synthesis, Kluwer Academic Publishers, Boston, 1984.
[3] Y. B. Dhong and C.P. Tsang, “High speed CMOS POS PLA using predischarged OR array and charge sharing AND array,” IEEE Trans. Circuits and Systems, Part II, vol. 39, pp. 557-564, Aug. 1992.
[4] J. Edmonds and E. L. Johnson, “Matching: a well-solved class of integer linear programs,” Combinatorial Structure and Their Applications, Gordon and Breach, New York, 1970, pp. 89-92.
[5] S. Iman, C. Y. Tsui, and M. Pedram, “PLA minimization for low power VLSI designs,” CENG Tech. Rep., Dept. of EE systems, University of Southern California, 1995.
[6] S. Posluszny et al., “Design methodology for a 1.0 Ghz microprocessor,” in Proc. IEEE Int. Conf. Computer Design, 1998, pp. 17-23.
[7] S. Posluszny et al., “Timing closure by design, a high frequency microprocessor design methodology,” in Proc. IEEE-ACM Design Automation Conf., 2000, pp. 712-717.
[8] Jan M. Rabaey, Digital integrated circuits: A design perspective, Prentice Hall, 1996.
[9] J. M. Tseng and J. Y. Jou, “Two-level logic minimization for low power,” ACM Trans. on Design Automation of Electronic Systems, pp.52-69, 1999.
[10] C. Wang et al., “A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS,” IEEE Trans. Circuits and Systems, Part I, vol. 46, pp. 857-861, July 1999.
[11] J. S. Wang, C. R. Chang, and Chingwei Yeh, “Analysis and design of high-speed and low-power CMOS PLA’s,” IEEE J. of Solid-State Circuits, vol. 36, pp. 1250-1262, Aug. 2001.
[12] N. Weste and K.Eshrahian, Principles of COMS VLSI design: A system perspective, 1 ed., Addison Wesly, 1985, pp. 371-372.

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