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研究生:鄭朝國
研究生(外文):Cheng Chao Kuo
論文名稱:1.25Gbps時脈與資料回復電路之設計
論文名稱(外文):1.25 Gbps Clock and Data Recovery Circuit Design
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Klaus Yung-Jane Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:80
中文關鍵詞:時脈資料回復鎖相迴路
外文關鍵詞:clockdatarecoveryPLL
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時脈回復電路(Clock Recovery Circuit),簡稱CRC (如具有資料回復,又稱CDR (Clock and Data Recovery)。應用於序列傳輸的接收介面,在較低的頻率應用下,通常是用數位電路來完成,最常見的是數位鎖相迴路 (DPLL)。然而在一些高速的應用上,例如光纖通訊系統,由於其傳輸的資料時脈頻率較高,所以通常都是用類比電路來完成,現有的產品大部分都是利用BJT 或 BiCMOS的製程,其操作頻段較高,對於雜訊抵抗能力較強,有比較好的performance,但是其缺點就是製程比較昂貴、整合不易且耗比較多的電流。近年來, CMOS的製程技術不斷的進步,因此CMOS CDR在學術期刊上廣為應用與發表,由於CDR電路常需要與其他路做整合的動作,所以CMOS低耗電、低價格、易整合的優點可以說是相當適合,我們可以利用電路的技術來克服元件本身的缺點,來達到SOC的目標。
隨著多媒體應用的普及,近幾年來通訊系統或其他數位資料的傳輸需求日益增大,使得時脈與資料回復電路具有相當大的應用空間並扮演更加重要的角色。
由於製程技術的快速進步,現今的互補式金氧半導體(CMOS)製程可以做許多高速的應用,並且具有低價與低耗電的優點。在此我們用0.35微米的數位互補式金氧半導體製程完成了一個以鎖相電路為基礎架構的時脈與資料回復電路。
在電路中我們使用一個兩級的環狀壓控震盪器來達到低耗電與高速的需求。此外並使用了一個對於輸入訊號之相位差有線性輸出之採樣保持(sample-and-hold)相位比較器。整個時脈與資料回復電路都是採用差動架構來降低來自電源的雜訊。除了採用類比的鎖向迴路電路來完成時脈的回復之外,我們並利用萃取出來的時脈與一個正緣觸發的高速類比D型正反器來做資料的回復。
由於低相位雜訊之壓控震盪器與全差動架構的採用,由本電路所產生之相位變異(Jitter)峰值到峰值(Peak-to-Peak)之模擬結果為45ps。核心電路的耗電量低至58.64毫瓦,整個晶片所使用的面積為0.75 × 0.6 平方厘米。

Clock and data recovery circuits (CDR) find wide application in digital communication systems. This thesis describes an analog PLL-based clock and data recovery circuit in a 0.35um digital CMOS technology and discusses each building block of phase lock loop circuits in detail.
The CDR we proposed operates at 1.25Gb/s which meets SONET OC-24 standard. To achieve a high speed with low power consumption, a 1.25GHz two-stage ring oscillator is introduced; it uses a fully differential architecture to reject noises from supply. A high speed sample-and-hold phase detector whose output pulsewidth is linearly proportional to the input phase difference is also depicted. Also an analog D flip-flop is described here as the decision circuit to regenerate data streams.
The circuit is designed with fully differential architecture and employs a low phase noise VCO to reduce jitter. The simulated jitter generation is 45 ps peak-to-peak for a PRBS sequence of length 223-1.
The core circuit dissipates a total power of 52.64mW from a 3.3V supply and occupies an area of 0.75 × 0.6 mm2.

1. Introduction…………………………………………………………. 1
1.1 Motivation…………………………………………………………… 1
1.2 Review on Prior Art……………………………………………… 3
1.3 Thesis Organization…………………………………………….. 6
2. Basic Concepts……………………..……………………………... 7
2.1 Optical Communication System…………………….…....…… 7
2.2 Role of Clock and Data Recovery Circuits...……....……10
2.3 Basic Principles of PLL-based CDR…………….…....…….12
2.3.1 General Considerations………………………..……..….. 12
2.3.2 Capture Range……………………………..……..…………. 14
2.3.3 Phase Noise…………..………………………...…………… 16
2.3.4 Jitter……….…………..……………..……………...…… 19
3. Design of Clock and Data Recovery Circuit………….…24
3.1 Introduction…………………..………..………………… 24
3.2 Voltage-Controlled Oscillator……………….….……. 25
3.3 Phase Detector………………..……………..…………… 34
3.4 Voltage-to-Current Converter…………….……………. 45
3.5 Loop Filter………...…..……………………………….. 46
3.5.1 PLL Stability………..………………………..…. 46
3.5.2 Second Order Low Pass Filter.……………..…. 48
3.6 Decision Circuit…………….....………………………. 51
3.7 Summary…………………...……….………………………. 53
4. Experimental Results……….…………………………………... 55
4.1 The Environment of Simulation…………………...…… 55
4.2 Simulation Results…………………..…………….…... 56
4.2.1 The Simulation Results of VCO………………... 56
4.2.2 The Simulation Results of PD + V-to-I Converter 59
4.2.3 The Simulation Results of Loop Filter………….. 61
4.2.4 The Simulation Results of Data Recovery…….... 63
4.3 Prototype Implementation…………..…..….…….….. 67
4.3.1 Design flow……………………………..………... 67
4.3.2 Measurement Cinsiderations…………….……... 68
4.3.3 Layout……………………………………………….. 69
4.4 Comparison and Summary……………………………..…… 71
5. Conclusions and Suggestions………...……………………….. 73
5.1 Conclusions…………….…………………………………… 73
5.2 Future Development and Suggestions....……………… 74
Bibliography………………..……………………………….. 75

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