隨著人們要求便利的特性許多攜帶型電子商品問世，低功率低電壓已是不可擋的趨勢，而運算放大器為類比電路中之一基本單元。所以設計低電壓端至端運算放大器為設計低電壓電路系統的基礎工作。
我們提出了兩種適用於超低電壓端至端運算放大器的電路結構。兩個電路都是以複合式輸入級為基礎，就是將N型和P型電晶體結合。第一個低電壓端至端運算放大器使用標準0.35毫米CMOS製程，原理是利用偵測輸入電壓的直流共模訊號作為調整輸入訊號直流偏壓的依據，當輸入級的電壓變動時我們也改變原先的直流偏壓，如此一來就能達到輸入級端至端和常數電導的要求。然後我們選擇了緩衝級的輸出級來作為輸出級，使得輸出電壓的擺幅也能達到端至端。這個運算放大器的單位增益頻寬為1.9MHz，迴轉率為0.8V/μs，晶片面積 0.089 mm2，頻寬-功率比為23.31 MHz/mW。有些規格比文獻上同樣架構的1V端至端運算放大器還好。另一個端至端運算放大器使用標準0.25毫米CMOS製程，我們將幾個關鍵的電晶體操作於弱反轉區，利用電晶體操作於弱反轉區時，電流和電導成線性關係，再利用電流鏡的技巧，來達成輸入級端至端和常數電導的要求。而回授式class-AB的輸出級除了能操作於低電壓使輸出能達到端至端外，也能精確的控制靜態電流，以降低功率的消耗。這個運算放大器的單位增益頻寬為1.8MHz，低頻增益為81dB，頻寬-功率比為32.73 MHz/mW。我們也將實驗數據和相關的運算放大器做了比較與討論。

The constraints on the design of CMOS operational amplifiers with rail-to-rail input and output range for extremely low supply voltage operation，are addressed. Two design approaches for amplifiers based on complementary input differential pairs are presented. The first，fabricated in a standard 0.35um CMOS process，realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifiers input range. Then we choose the class-AB output stage to ensure the output swing is rail-to-rail. This Op-amp yields an unit-gain frequency of 1.9MHz，slew rate of 0.8V/us，chip area 0.089 mm2，and bandwidth-power ratio of 23.31 MHz/mW. Some specifications are even better than the of the proposed 1V rail to rail Op-amp. Another Op-amp，fabricated in a standard 0.25um CMOS process， lets several critical transistors in weak inversion region. The feedback class-AB is used to allow further lowering of operating voltage. This Op-amp had an unit-gain frequency of 1.8MHz，and DC gain of 81dB with bandwidth-power ratio of 32.73 MHz/mW. Experimental results are provided and the corresponding performance are discussed and compared.

1.Introduction………………………………………………………..…...1
2.Considerations and Design Issues of Low-voltage Op-amps..4
2.1 Classification of CMOS low-voltage
circuits………………..5
2.2 Design issues of rail-to-rail input
stage…………………………....6
2.2.1 Complementary input pairs…...
………………………….....7
2.2.2 MOSFETs work in weak inversion………………….
……...9
2.2.3 The constant-gm control
circuits………………………......10
2.2.4 The summing circuit with folded cascoded
structure…..….11
2.3 Design issues of the rail-to-rail output
stage……………………..….13
2.3.1 Class AB output
stages…………………………………….14
2.3.2 Output stage with feedforward class-AB
control………….15
2.3.3 Output stage with feedback class-AB
control……………..18
2.4 Summary…………………………………………………………
… 22
3. Design of 1V constant gm rail-to-rail Op-amp fabricated with a standard 0.35um CMOS process………………………...24
3.1 Design of the rail-to-rail input
stage…………………………..25
3.1.1 The principle of the rail-to-rail input
stage…...…………...25
3.1.2 Design of the rail-to-rail input
stage…………….……...27
3.1.3 Level-Shift Current Generator……………..
……….28
3.1.4 The entire rail-to-rail input
stage……………..………..30
3.2 Design of the rail-to-rail output
stage…………………….………....32
3.3 Chip organization and layouts…………………..
……………..….33
3.4 Conclusions……………………………………………………….
…34
4. Design of 1V constant gm rail-to-rail Op-amp fabricated with a standard 0.25um CMOS process…………………….35
4.1 Design of the rail-to-rail input stage………………..36
4.2 Design of rail-to-rail output
stage…………………………....39
4.3 Overall topology and frequency
compensation………………..….43
4.4 Chip organization and layouts……….…………………….
…45
5. Test Systems and The Measured Results……………………...48
5.1 The test result of the 1V rail-to-rail Op-amp
fabricated with a standard 0.35um CMOS
process……………………………………………..48
5.2 The test result of the 1V rail-to-rail Op-amp
fabricated with a standard 0.25um CMOS process….
……………………………...…………...57
6. Conclusions and Future Work………………………..…...65

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