臺灣博碩士論文加值系統

類比積體電路的自我測試一直被認為是相當困難的課題, 因為要決定一個類比電路是否通過測試與數位測試法不同, 必須由觀察特定之類比信號是否落在一個特定範圍, 而非一決定值來確定。此外, 類比信號可以是非常小, 故對測試環境非常敏感, 非常遺憾地, 大量的噪音和干擾源存在於類比電路本身, 混合信號 (Mixed-Signal) 晶片, 和系統之中。 所以在做類比測試時必須花費很大的功夫來抑制和隔離測試環境的干擾源。 同時由於類比電路對製程變化相當敏感, 一個好的類比自我測試電路必須比待測電路對製程變化的敏感度更小, 以避免因自我測試電路本身的問題而造成誤判。
傳統上, 是利用詳盡的功能測試 (Functional Test) 來做類比測試。雖然功能測試可以進行精確且詳盡的類比量測, 但是它是一個昂貴的測試方法因為它通常需要高功能且昂貴的混合信號自動測試設備, 而且類比測試時間比較長。 因此, 測試成本甚至有可能會比製造成本更高。 現代混合信號系統單晶片 (System-on-a-chip) 由於它的可觀察點及可控制性被限制, 使得它的測試更困難。 此外, 儘快上市的壓力使得設計者必須快速並準確的診斷原型以便及時正確地修改設計。 因而, 我們需要一個有效並且低成本的類比自我測試法。
在本文中, 我們提出以 Sigma-Delta 調變法為基礎的類比自我測試法來解決以上的需要。 此類比自我測試法是一種功能測試法, 故可以進行精確且詳盡的類比量測, 它利用 Sigma-Delta 調變法來產生激發訊號、 抽取並數位化待測物的響應以降低成本, 實作結果證明非常有效, 此法尤其適用於取樣系統因為不需要佔面積的反-假頻 (anti-aliasing) 濾波器。針對特定的應用和功能測試, 我們能夠最佳化地選擇適用的 Sigma-Delta 調變器。 我們並導論出設計有效測試的準則。
對於需要更高精度或者更寬帶寬的應用, 可以使用高階的 Sigma-Delta 調變器。 我們提出一高階 Sigma-Delta 調變器, 由許多一階或二階的調變器串接而成。它具有低硬體複雜性, 高穩定性, 不需要高規格的電路, 並適合在不同的超頻取樣率 (OSR) 下操作， 可視待測物的特性在準確度和頻寬中做取捨的特性，所以特別適用於所提出之類比自我測試法。
我們使用 MOSIS , 0.35微米 CMOS 製程製作了測試晶片, 其中含有一個 Fleischer — Laker的二階低通濾波器作為待測物。我們從外部提供經S-D 調變之位元流 (bit-stream) 至一個內建的單位元數位-類比轉換器以提供待測物設計好的類比激發訊號。 對於每一個測試項, 由一-, 二-, 四-階軟體 S-D 調變器合成不同位元流, 來比較它們的表現。 類比響應則由一-, 二-, 五階硬體 S-D 調變器負責轉換成數位訊號以分析測試結果。
我們並提出低成本的可全數位測試 S-D 調變器電路, 經由增加少許的電路, 即可免去需要昂貴的類比自動測試機校正數位化響應抽取器的困擾。
測量結果顯示一階數位化響應抽取器 (Analog Response Extractor) 對於頻率響應測試最為合算。二階數位化響應抽取器適用於一般低成本應用。五階數位化響應抽取器提供最好的性能, 但是需要比較高的硬體成本。
使用多位元的 S-D 調變器能夠進一步提升數位化響應抽取器的功能。我們提出位元規劃法以減少硬體花費並減輕對電路的需求。 這些設計規則並經由行為模式模擬證實。

摘 要 ……………………………………………………………… I
誌 謝 ……………………………………………………………… III
目 錄 ……………………………………………………………… IV
第一章 概論 ……………………………………………………….. V
第二章 以 S-D 調變法為基礎之低成本類比自我測試法 ……... VI
第三章 串接式高階 S-D 調變器 ……………………………….. VII
第四章 選擇適用於內建式類比自我測試的高階S-D調變器架構. VIII
第五章 五階串接式 S-D 調變器的實現 ……………………….. Ⅸ
第六章 多位元 S-D 調變器 …………………………………….. Ⅹ
第七章 結論與未來之研究 ………………………………………. XI
英文附錄及參考文獻………………………………………………... XII

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