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[1] C. Ho, “Gate Oxide Scaling Limits and Projection”, IEDM’96., pp. 319-322. [2] C. C. Chen, et al. , Appl. Phys. Lett., vol. 74, pp. 3708-3710 (1999). [3] Tung Ming Pan et al, Appl. Phys. Lett. vol. 78 p. 1439.(2001) [4] Jack C. Lee,Ultra-Thin Gate Dielectrics and High-K Dielectric, IEEE EDS Vanguard Series of Independent short Course, p. 202( 2001) [5] B. H. Lee, et al.,IEDM Tech. Dig . p.39(2000) [6] N. Zhan , et al., Electron Devices Meeting, 2002. Proceedings . 2002 IEEE Hong Kong , 2002 Page(s): 43 -46 [7] W. Zhu, et al.,IEDM Tech.Dig.,p.463(2001) [8] J.H. Lee, et al., IEDM Tech. Dig.,p.84 (2002) [9] H.J. Cho, et al. IEEE Electron Device Letters , Volume: 23 Issue: 5 , May 2002 Page(s): 249 -251 [10] C.H. Choi, et al. IEDM Tech. Dig.,p.857,(2002) [11] C.S. Kang, et al., Symp .On VLSI Tech,p.146(2002) [12] S.J. Clarke ,et al. Journal of Solid State Chemistry 146 ,p.399(1999) [13]余樹楨著,“晶體之結構與性質”,渤海堂文化事業有限公司,中華民國八十 九年五月再版。 [14] I. Polishchuk et al. IEEE Transaction On Device and Materials Reliability , vol.1, No.1 March 2001 [15] K. J. Hubbard et al . ,J. Mater. Res.11,2757(1996) [16] G. B. Alers et al .,APL 73 ,1517(1998) [17] J . Robertson , IWGI Tokyo ,p76 (2001) [18] B.H. Lee et al.IEDM,133,(1999) [19] T. Yamaguchi et al. IEDM Tech.Dig,p.621 (2002) [20] Y. Jeon et al. IEDM ,p.797(1998) [21] 莊達人主編, “VLSI製造技術”, 高立圖書有限公司,2002年五版修訂 [22] 汪建民主編, “材料分析”, 中國材料科學學會, 2001再版 [23] Jack C. Lee,IEEE EDS Vanguard Series of Independent short Course, p. 202, 2001 [24] ITRS ,SIA, San Jose, CA ,1999 [25] T. P. Ma, IEEE Trans. Electron Devices, vol. 45, p. 680, March 1998. [26] S. Gopalan et al. ,DRC p.195(2002) [27] C. S. Kang et al. IEDM Tech.Dig,p.865( 2002) [28] B. H. Lee et al. Appl . Phys . Lett . 76 p.1926 (2000) [29] H. F. Luan et al. IEDM Tech. Dig,p.141(1999) [30] B. H. Lee et al. IEDM Tech. Dig,p.39(2000) [31] R. Nieh et al. IWGI (2001) [32] Tokyo , R. Choi et al. Symp VLSI tech p.193(2001) [33] L. Kang, et al., IEEE Electron Device Lett. 21, 181, 2000. [34] K. Yamamoto, et al., Appl. Phys. Lett. 81, 2053, (2002) [35] S. M. Sze, Semiconductor device physics and technology, 2nd Ed., John Wily and Sons,p.442.1985. [36] H. F. Luan, et al., IEDM Tech.Dig, p.609(1998), [37] H. F. Luan, , IEDM Tech.Dig, p. 141(1999) [38] L. Manchanda et al. ,IEDM Tech . Dig. ,p.23(2000) [39] J. M. Hergenrother et al .,IEDM Tech . Dig. ,p.51(2001) [40] W. Zhu et al .,IEDM Tech . Dig. ,p.463(2001) [41] J. H. Lee, et al .,IEDM Tech . Dig. ,p.645(2000) [42] J.H. Lee, et al., Symp .On VLSI Tech,p.84(2002) [43] P.J. Chen, et al., Symp .On VLSI Tech,p.192(2002) [44] C. W. Yang et al., Electronics Letters 26th September 2002 Vol.38 No.20
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