臺灣博碩士論文加值系統

本論文描述了一個工作在1.5伏特，而輸出頻率範圍為5.02GHz~5.47GHz之CMOS頻率合成器，我們利用鎖相迴路的基本架構來完成一個全積體化的頻率合成器，其中包含相位/頻率偵測器、電荷充放電路、低通濾波器、5GHz壓控振盪器及除頻器電路。相位/頻率偵測器用來偵測參考訊號與內部除頻訊號間的相位差及頻率差，產生UP與DN的充放電數位控制訊號，後級的電荷充放電路把UP與DN的數位訊號轉成相對的電壓差，用來調變壓控振盪器的振盪頻率。使用二階低通濾波器來濾掉電荷充放電路輸出的高頻訊號成分。壓控振盪器部分則採用LC-tank的振盪器架構，把整個振盪頻率提高至5GHz左右。除頻器是使用注入式鎖定除頻器與可程式除頻器所組合而成，其中注入式鎖定除頻器能夠將5GHz的輸出頻率除以二，而可程式除頻器其可除頻率範圍則為128~511。此鎖相迴路系統是使用TSMC 0.18μm 1P6M Triple Well的技術來做設計，而整體的功率消耗約為21.53mW，鎖定時間則約為5us。

In this thesis, we design a 1.5V CMOS frequency synthesizer with output frequency 5.02GHz~5.47GHz, which is composed of a phase/frequency detector (PFD), a charge pump circuit (CP), a low pass filter (LF), a 5GHz voltage controlled oscillator (VCO) and frequency divider (FD), based on simple phase-locked loop (PLL) system structure that has been fully integrated on a single chip. The PFD detects the phase and frequency error between the reference signal and the divider output, and then produces the UP and DN signals. Next stage, the CP transfers the digital signals, UP and DN, to a relative voltage signal to modulate the output frequency of the VCO. The second-order LF filter is designed to filter off the part of high frequency in output signal of the CP. The VCO is designed with the LC-tank structure and the output range up to 5GHz. The FD employs injection lock frequency divider and programmable divider, which the injection lock frequency divider can work in 5GHz high frequency and the programmable divider can divide by 128~511. The PLL is design and simulated with the TSMC 0.18μm 1P6M Triple Well technology. The power dissipation of the PLL is about 21.53mW and the lock time is about 5us.

目錄
第一章 緒論……………………………………………………………1
1-1 研究動機………………………………………………………1
1-2 論文組織………………………………………………………2
第二章 鎖相迴路的系統分析…………………………………………3
2-1 簡介……………………………………………………………3
2-2 鎖相迴路的系統分析…………………………………………3
2-2-1 一階迴路濾波器………………………………………………5
2-2-2 二階迴路濾波器………………………………………………7
2-3 鎖相迴路的雜訊分析…………………………………………9
2-4 鎖相迴路的設計考量…………………………………………10
第三章 相位頻率偵測器與電荷幫浦以及迴路濾波器設計…………12
3-1 相位頻率偵測器………………………………………………12
3-1-1 電路架構與原理………………………………………………12
3-1-2 相頻偵測器模擬結果…………………………………………14
3-2 電荷幫浦與迴路濾波器設計…………………………………16
3-2-1 簡介……………………………………………………………16
3-2-2 傳統電荷幫浦…………………………………………………17
3-2-3 改良式電荷幫浦………………………………………………18
3-2-4 電荷幫浦模擬結果……………………………………………20
3-2-5 迴路濾波器的參數設定………………………………………21
第四章 前置除頻電路與可程式除頻電路設計………………………22
4-1 前置除頻電路設設……………………………………………22
4-1-1 簡介……………………………………………………………22
4-1-2 電路架構與原理說明…………………………………………22
4-2 可程式除頻電路設計…………………………………………30
第五章 壓控振盪器電路設計…………………………………………33
5-1 電路原理說明…………………………………………………33
5-1-1 簡介……………………………………………………………33
5-1-2 負轉導(Negative -Gm)振盪器………………………………35
5-1-3 雜訊濾除技巧…………………………………………………40
5-2 相位雜訊分析…………………………………………………41
5-2-1 簡介……………………………………………………………41
5-2-2 相位雜訊………………………………………………………41
5-2-3 線性非時變的Lesson相位雜訊模型分析……………………42
5-2-4 線性時變的相位雜訊模型分析………………………………44
5-2-5 其他時變的影響………………………………………………53
5-2-5-1 Cyclostationary 雜訊源……………………………………53
5-2-5-2 電壓相依電容…………………………………………………54
5-2-6 振幅響應………………………………………………………54
5-2-7 時變以及非時變相位雜訊模型之間的比較及其相關性……57
5-3 模擬結果與設計考量…………………………………………58
5-3-1 模擬結果說明…………………………………………………58
5-3-2 結論……………………………………………………………64
第六章 頻率合成器的實現……………………………………………66
6-1 頻率合成器的模擬結果………………………………………66
6-2 建議以及未來研究方向………………………………………68
參考文獻 …………………………………………………………………69

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