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研究生:吳信忠
研究生(外文):Hsin-Chung Wu
論文名稱:CMOS鎖相迴路架構之頻率合成器研究
論文名稱(外文):Study on CMOS PLL-Based Frequency Synthesizer
指導教授:張勝良
指導教授(外文):Sheng-Lyang Jang
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:86
中文關鍵詞:互補式金氧半場效電晶體鎖相迴路頻率合成器
外文關鍵詞:CMOSPLLFrequency Synthesizer
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現今對無線通訊服務的需求急速成長,使得射頻晶片朝向無線系統所要求的低功率、低成本以及高整合性能邁進。藉由互補式金氧半場效電晶體製程尺寸縮減技術能夠更有效地利用以改進無線射頻收發機和頻率合成器的整合,來對功率損耗及成本做更進一步的改進。頻率合成器用來產生一個本地振盪器頻率,為無線通信裝置是主要構件之一,因為頻率合成器影響整個無線系統的效能,它必需要有高效能和低相位雜訊以及較低的旁頻帶突波。
在本文中,利用台積電提供 0.35 m CMOS 製程來設計頻率合成器。此合成器採用整數-N 鎖相迴路為基本架構,一些關鍵區塊的電路設計包括相位頻率檢測器、充電幫浦、被動迴路濾波器、電壓控制震盪器以及一可規劃的除頻器更詳細討論於本文中。最後,對各區塊電路以及整個鎖相迴路和頻率合成器閉迴路作模擬;也完成環型震盪器及LC共震腔震盪器量測,其震盪器可利用於 GSM(900MHz)及 Bluetooth(2.4GHz)。

The recently rapid growth in demand for wireless communications services has been a strong motivation for designing more highly integrated RFICs with low operating voltage, power, and cost. Scaled CMOS technologies can be more effectively utilized to improve the integration level of the RF transceivers and synthesizers with the result of further improvements in power dissipation and cost. A frequency synthesizer, used to generate a local oscillator (LO) frequency, is one of the major building blocks for wireless communications devices. Since the synthesizer influences the performance of the overall wireless systems, it should have high performance, specifically low phase noise and low sideband spurs.
In this thesis, a frequency synthesizer is designed in TSMC 0.35 m CMOS process. This synthesizer is based on an integer-N phase-locked loop. The design of some key blocks includes a phase frequency detector, a charge pump, an integrated passive loop filter, a VCO, and a programmable frequency divider is discussed in more detail. Finally, we obtained simulation results of each blocks of phase-locked loop and frequency synthesizer, and finished overall closed loop simulation. We also finished the measurement of ring oscillator and LC-tank VCO, which can be applied in GSM (900MHz) and Bluetooth system (2.4GHz).

Contents
1 Introduction 1
1.1 Research Motivation••••••••••••••••••••••••1
1.2 Thesis Organization••••••••••••••••••••••••4
2 Concepts of Frequency Synthesizer 5
2.1 Frequency Synthesizer Specifications •••••••••5
2.1.1 Tuning Range and Minimum Step Size••••••••5
2.1.2 Settling Time ••••••••••••••••••••••••••7
2.1.3 Spurious Signals •••••••••••••••••••••••8
2.1.4 Phase Noise••••••••••••••••••••••••••••9
2.2 Phase-Locked Loop Fundamentals•••••••••••••••11
2.3 The Behavior Models of Functional Blocks••••••13
2.3.1 Phase Frequency Detector (PFD) ••••••••••14
2.3.2 Charge Pump (CP)•••••••••••••••••••••••16
2.3.3 Loop Filter (LPF)••••••••••••••••••••••18
2.3.4 Voltage Controlled Oscillator (VCO) •••••25
2.3.5 Frequency Divider (FD)•••••••••••••••••27
3 CMOS Frequency Synthesizer Realization 29
3.1 Phase Frequency Detector ••••••••••••••••••29
3.2 Charge Pump •••••••••••••••••••••••••••••35
3.3 Voltage Controlled Oscillator •••••••••••••38
3.3.1 Ring Oscillator•••••••••••••••••••••••38
3.3.2 LC- tank Oscillator•••••••••••••••••••44
3.4 Frequency Divider•••••••••••••••••••••••••48
3.4.1 Introduction••••••••••••••••••••••••••48
3.4.2 Dual-Modulus Prescaler••••••••••••••••50
3.4.3 Program Counter/Swallow Counter••••••••56
4 Simulation Results, Chip Implementation and Measurement 60
4.1 Introduction•••••••••••••••••••••••••••••60
4.2 The 2.4GHz Phase Locked Loop•••••••••••••••60
4.2.1 The PFD, Charge Pump, and Loop Filter••••61
4.2.2 The LC-tank VCO and Frequency Divider••••63
4.2.3 Closed Loop Simulation••••••••••••••••••••••••••••••••••••65
4.2.4 Chip Layout and Performance•••••••••••••••••••••••••••••••••••67
4.2.5 Measurement••••••••••••••••••••••••••68
4.3 The 900MHz Frequency Synthesizer•••••••••••70
4.3.1 The Ring Oscillator•••••••••••••••••••70
4.3.2 The Pulse-Swallow Divider••••••••••••••70
4.3.3 Closed Loop Simulation•••••••••••••••••74
4.3.4 Chip Layout and Performance•••••••••••••74
4.3.5 Measurement•••••••••••••••••••••••••••78
4.4 The Bluetooth Frequency Synthesizer••••••••••80
4.4.1 Closed Loop Simulation••••••••••••••••••80
4.4.2 Chip Performance•••••••••••••••••••••••83
5 Conclusion 85

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