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[1] P. R. Gray and R. G. Meyer, “Future directions in silicon ICs for RF personal communication,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp.83-90, May 1995, [2] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice-Hall, 1998. [3] D. Leenaerts, J. Tang and C. Vaucher, Circuit Design for RF transceivers. Kluwer Academic Publishers, Boston, 2001. [4] B. Razavi, “A 900 MHz/1.8GHz CMOS Transmitter for Dual-Band Application,” IEEE J. Solid-State Circuits, vol.34, no.5, pp.573-579, May 1999. [5] B. Razavi, “A Study of Phase Noise in CMOS Oscillator,” IEEE J. Solid-State Circuits, vol.31, pp.331-343, March 1996. [6] F. M. Gardner, Phase lock Techniques. 2nd ed. Wiley, New York, 1979. [7] F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. communications, vol.28, pp.1849—1858, Nov 1980. [8] W. F. Egan, Frequency Synthesis by Phase Lock. John Wiley & Sons, New York, 1981. [9] W. O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor Application Note 1001, May 1996. [10] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, New York, 2000. [11] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE J. Solid-State Circuits, vol. SC-27, pp.1599-1607, November 1992. [12] D. K. Jeong et al., “Design of PLL-Based Clock Generation Circuits,” IEEE J. Solid-State Circuits, vol. SC-22, pp.255-261, April 1987. [13] T. H. Lee, Hirad Samavati, H. R. Rategh, “5-GHz CMOS Wireless LANS,” IEEE Trans. Microwave Theory and Techniques, vol.50, no.1, pp.268-280, January 2002. [14] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops Circuits and Systems,” 1999. ISCAS '99. Proceed the 1999 IEEE Int. Symp,vol.2, pp.545-548, Jul 1999. [15] Y. Fouzar, M. Sawan, Y. Savaria, “CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL,” Proc. 43rd IEEE Midwest Symp. Circuits and Systems, Lansing MI, pp.948 -950, Aug 2000. [16] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-μm CMOS, ” IEEE J. Solid-State Circuits, vol.34, pp.586-591, May 1999. [17] Dan H. Wolaver, Phase-locked loop circuit design. Prentice-Hall, Englewood Cliffs, N.J, 1991. [18] A. Hajimiri and T. H. Lee, “Phase Noise in CMOS differential LC Oscillator,” Symp. on VLSI circuits, pp.49-52,May 1998. [19] A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillator,” IEEE J. Solid- State Circuits, vol.33, no.2, pp.179-194, Feb 1998. [20] C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz Frequency synthesizer in 0.4-um CMOS Technology,” IEEE J. Solid-State Circuits, vol.35, no.5, pp.788-794, May 2000. [21] H. Darabi, S. Khorram, H. M. Chien, M. A. Pan, S. Wu, S. Moloudi, J. C. Leete, J. J Rael, M. Syed, R. Lee, B. Ibrahim, M. Rofougaran, and A. Rofougaran “A 2.4-GHz CMOS Transceiver for Bluetooth,” IEEE J. Solid-State Circuits, vol.36, no.12, pp.200-201, December 2001. [22] B. Razavi, K. F. Lee, and R. H. Yan, “A 13.4-GHz CMOS Frequency Divider,” Int. Solid-State Circuits Conf., pp.224-225, February 1994. [23] P. Larsson and C. Svensson, “High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler,” IEEE J. Solid-State Circuits, vol.31, pp.744-748, May 1996. [24] C. M. Hung, Brian A. Floyd and Kenneth K. O, “A fully integrated 5.35-GHz CMOS VCO and a Prescaler,” IEEE Trans. Microwave Theory and Techniques, vol.49, pp.17-22, January 2000. [25] Jan Craninckx and Michel S. J. Steyaert, “A 1.8-GHz CMOS low-phase-noise voltage controlled oscillator with prescaler,” IEEE J. Solid-State Circuits, vol.30, no.12, pp.1474—1482, December 1995. [26] J. K. Qiu, “Design and realization CMOS RF Frequency synthesizer,” MS Thesis, Dpt. of Electrical Engineering, National Taiwan University, June 2001.
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