跳到主要內容

臺灣博碩士論文加值系統

(98.84.25.165) 您好!臺灣時間:2024/11/10 00:40
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:黃漢城
研究生(外文):Han-Cheng Huang
論文名稱:低成本的垂直正交掃描鏈設計
論文名稱(外文):Low Overhead on RTL Orthogonal Scan Chain Design
指導教授:蔡加春蔡加春引用關係李文達李文達引用關係
指導教授(外文):Chia-Chun TsaiWen-Ta Lee
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦通訊與控制研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:60
中文關鍵詞:掃描鏈高階測試設計垂直正交掃描鏈低成本可測性設計
外文關鍵詞:Scan ChainRTL test designOrthogonal Scan ChainLow OverheadDFT
相關次數:
  • 被引用被引用:0
  • 點閱點閱:466
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在製程的提昇、系統單晶片(SoC)技術日益成熟的雙重壓力下,單一晶片所包含電晶體數量越來越大,也使得測試成本與日遽增,可測性的設計(DFT)的要求也就在各類超大型積體電路中出現。在數位電路中,掃描鏈(Scan Chain)的設計是最基本的可測性設計,傳統的掃描鏈是在每個暫存器前面加上一個多工器,用多工器將暫存器串成一條記憶鏈。這種設計會造成電路的面積增加,且傳統的掃描鏈為了減少額外的接腳之成本,會將掃描鏈的個數降到最低,但這會造成掃描鏈過長而增加測試的時間之成本。
本論文針對此一部份,提出高階的RTL設計中插入垂直正交掃描鏈。首先,分析高階的Verilog設計建立資料路徑圖,並找出最省面積的垂直正交資料路徑作為掃描鏈的資料路徑,此設計並不增加額外的接腳且可降低掃描鏈的面積,接著利用堆疊的方式使多條資料路徑同時存在,而掃描鏈的長度也相對變短。我們以ITC’99的Benchmarks作驗證。結果顯示,相較於低階標準掃描鏈、高階Random order掃描鏈與高階Functional order掃描鏈,垂直正交掃描鏈有效降低了13.8%、8.4%與5.1%的測試面積。在掃描鏈的長度方面,亦縮短了21%~45%。
As the IC (Integrated Circuit) industry continuously increases the number of transistors in a chip, the SOC (System on a chip) finally becomes a reality. At the same time, the testing cost of a chip increase well, so DFT (Design for Testability) features become affective for all VLSI. Among those DFT techniques, scan chain is basic design. Conventional scan chain has long test time and large area overhead.
In this thesis, we proposed a low-overhead orthogonal scan chain embedded into the Register Transfer Level (RTL) design described by Verilog. We first construct the data path graph from the embedded scan chain and then find all the orthogonal scan paths with minimum cost. These paths share with original data paths. Finally, we create a stack form to place scan paths to manger the IO and reduce the scan chain length as well as reduce the test cycle and save test cost. We conduct experiments on our methods with ITC’99. The results show our RTL orthogonal scan chain approach can save up to 13.8%, 8.4%, and 5.1% in area overhead than the standard gate-level scan, random order RT-level scan and function order RT-level scan, respectively. In test time, RTL orthogonal scan chain can save up 21%~45% clock cycles to test one pattern.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 v
圖目錄 vi
第一章 簡介 1
1.1研究動機 1
1.2研究目標 2
1.2論文結構 3
第二章 掃描鏈背景知識 4
2.1數位測試的目標 4
2.2測試技術的簡介 5
2.2.1 回饋測試技術 5
2.2.2 掃描技術 6
2.2.3 自我測試系統 7
2.2.4 測試介面 8
2.3掃描鏈的測試原理 8
2.4掃描鏈的研究 10
2.4.1 使用標準的測試元件作測試 10
2.4.2 利用原來組合邏輯的資料路徑作為掃描鏈的資料路徑 12
2.4.3 在高階行為描述加入掃描鏈 14
2.4.4 在高階行為描述中分享資料路徑作為掃描路徑 16
第三章 垂直正交掃描鏈設計 19
3.1高階掃描鏈的設計 19
3.2系統的介紹 20
3.3暫存器之擷取 21
3.4資料路徑的分析及建立資料路徑圖 26
3.4.1 延遲性的資料路徑 26
3.4.2 選擇性的資料路徑 27
3.4.3 其餘的資料路徑 29
3.4.4 建立資料路徑圖 31
3.5使用貪婪演算法找出低面積成本的資料路徑 33
3.6利用堆疊的方式修正資料路徑 36
第四章 模擬及合成實驗結果 47
4.1測試例子 47
4.2模擬流程圖 47
4.3模擬結果及比較 49
4.4數位濾波器與數位座標旋轉器之模擬結果及比較 52
第五章 結論與未來展望 56
5.1結論 56
5.2未來展望 56
參考文獻 57
[1] S.M. Reddy and R. Dandapail, “Scan Design Using Standard Flip-Flops,” IEEE Design Test of computers, Feb. 1987, pp. 52-54.
[2] Chih-Chang Lin, M.T.-C. Lee, Marek-Sadowska, and Kuang-Chien Chen, “Cost-free scan: a low-overhead scan path design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 9, Sep. 1998, pp. 852-861.
[3] Chih-Chang Lin, Marek-Sadowska, Kwang-Ting Cheng and M.T.-C. Lee, “Test-point insertion: scan paths through functional logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No 9, Sep. 1998, pp. 838-851.
[4] C. Aktouf, H. Fleury and C. Robach, “Inserting scan at the behavioral level,” IEEE Design & Test of Computers, Vol. 17, No 3, Jul/Sep 2000, pp. 34-42.
[5] M.T.-C. Lee, High Level test synthesis of digital VLSI circuits, Artech House, 1997.
[6] Yu Huang, Chien-Chung Tsai, N. Mukherjee, O. Samman, D. Devries, Wu-Tung Cheng and S.M. Reddy, “On RTL scan design,” IEEE International Test Conference, 2001, pp. 728-737.
[7] T. Asaka, S. Bhattacharya, S. Dey and M. Yoshida, “H-SCAN+: a practical low-overhead RTL design-for-testability technique for industrial designs,” IEEE International Test Conference, Nov. 1997, pp. 265-274.
[8] S. Bhattacharya and S. Dey, “H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads,” IEEE International Test Conference, May 1996, pp. 74-80.
[9] S. Sapiro and R. Simith, Handbook of Design Automation, CAE System, Inc. 1984.
[10] Juan Carlos Lopez, Roman Hermida and Walter Geisselhardt, Advanced Techniques for Embedded Systems Design and Test, Kluwer Academic Publishers, 1998.
[11] H. Farshbaf, M. Zolfy, S. Mirkhani and Z. Navabi, “Fault simulation for VHDL based test bench and BIST evaluation,” IEEE Test Symposium, 2001, pp. 396-401.
[12] V.D. Agrawal, C.R. Kime, and K.K. Saluja, “A tutorial on built-in self-test. I. Principles,” IEEE Design & Test of Computers, Vol. 10, No 1, Mar. 1993, pp. 73-82.
[13] B. Reeb and H.J. Wunderlich, “Deterministic pattern generation for weighted random pattern testing,” IEEE European Design and Test Conference, Mar. 1996, pp. 30-36.
[14] R. Kapur, S. Patil, T.J. Snethen and T.W. Williams, “A weighted random pattern test generation system,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, Aug 1996, pp. 1020-1025.
[15] J. Savir, “Reducing the MISR size,” IEEE Transactions on Computers, Vol. 45, No. 8, Aug 1996, pp. 930-938.
[16] E.J. Marinissen, R. Kapur and Y. Zorian, “On using IEEE P1500 SECT for test plug-n-play,” IEEE International Test Conference, 2000, pp. 770-777.
[17] J.E. Kadaras, “A chip to embedded system test process using IEEE 1149.1 boundary scan,” IEEE International Electro Conference, May 1994, pp. 728-732.
[18] Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang and Hsiao-Ping Lin, “A hierarchical test methodology for systems on chip,” IEEE Micro Journal, Vol. 22, No. 5, 2002, pp. 69-81.
[19] E.J. Marinissen, S.K. Goel and M. Lousberg,” Wrapper design for embedded core test,” IEEE International Test Conference, 2000, pp. 911-920.
[20] B.I. Dervisoglu, “A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers,” IEEE Design Automation Conference, 2001, pp. 53-58.
[21] X.U. Zheng, Verilog Hardware Description Language and physical Design, Taipei, SIM, 2002.
[22] Wen-Sheng Chiang, Efficient VLSI Architectures with Low Hardware Cost for Discrete Wavelet Transform, Master Thesis, National Taipei University of Technology, 2002.
[23] Ray Andraka, “A survey of CORDIC algorithms for FPGAs,” Sixth international Symposium on Field Programmable Cate Arrays, Feb. 1998, pp. 191-200.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top