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研究生:羅有龍
研究生(外文):Yu-Lung Lo
論文名稱:具快速鎖定及寬頻操作之延遲鎖定迴路設計
論文名稱(外文):Design of Delay-Locked Loop with Fast-Lock and Wide-Range Operation
指導教授:鄭國興鄭國興引用關係
指導教授(外文):Kuo-Hsing Cheng
學位類別:碩士
校院名稱:淡江大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:78
中文關鍵詞:延遲鎖定迴路寬頻延遲鎖定迴路快速鎖定混合式時間數位轉換器
外文關鍵詞:DLLWide-Range DLLFast-LockMixed-ModeTDC
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當超大型積體電路設計在速度的效能上快速的增加,許多的設計在於強調減少時脈歪斜與抖動,延遲鎖定迴路及鎖相迴路,廣泛的應用於減少時脈歪斜與抖動所造成的缺陷;例如在高效能的應用上如微處理器、記憶體積體電路及通訊晶片時脈的產生。在時脈抖動上延遲鎖定迴路有較佳的表現,是由於延遲鎖定迴路不會像鎖相迴路有時脈抖動累積的特性,而且具穩定性及在數位電路上易於被實現,所以,一般而言,若不需要倍頻輸出的應用,延遲鎖定迴路將會是更具吸引力被設計及應用。在第三章中,將介紹一個利用電源重置電路作快速鎖定的延遲鎖定迴路,所提出的架構是以0.35微米的互補式金氧半製程製造,電路面積為1234×1234平方微米,其中包含輸入及數位輸出的電路。操作頻率範圍是100至190MHz,當輸入頻率為100MHz時,所量測的峰值抖動及方均根抖動分別是65ps及11.9ps;當輸入頻率為190MHz時,所量測的峰值抖動及方均根抖動分別是50ps及10.6ps,最大的鎖定時間為43個時脈週期。在第四章中,將介紹一個具快速鎖定及寛頻操作之延遲鎖定迴路,電路架構中使用混合式的時間數位轉換器的技巧來實現相位選擇器,並配合啟動電路及粗調電路,使之具有快速鎖定的功能。多段式控制的壓控延遲線,可使延遲鎖定迴路有更寛的操作頻率範圍,並且利用數位式控制的充電泵可使延遲鎖定迴路兼具頻寛追蹤(Bandwidth Tracking)及低時脈抖動的特性。所提出的架構是以0.25微米的互補式金氧半製程製造,操作頻率是40至300MHz,而且能夠鎖定在一個週期並產生十組平均等分的相位輸出,其最大的鎖定時間是22個時脈週期。
As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLL’s) and delay-locked loops (DLL’s) have been typically employed in microprocessors, memory interfaces, and communication IC’s for the generation of on-chip clocks. In general, if there is no need for frequency multiplication, DLL’s would be more attractive than PLL’s because they are more stable and easy to implement together with digital circuits and don’t exhibit the jitter accumulation characteristic as PLL’s do. Therefore, the DLL’s offer better jitter performance than PLL’s.
In chapter 3, a fast-lock DLL with power-on reset circuit has been fabricated in TSMC 0.35μm 1P4M N-well CMOS process with a 3.3V power supply voltage. The chip area is 1234×1234 µm2 including input and output digital buffers. From the measurement results, the proposed DLL can operate correctly from 100MHz to 190MHz. When the input clock frequency is 100MHz, the measured output clock peak-to-peak jitter and rms jitter are 65ps and 11.9ps, respectively. And when the input clock frequency is 190MHz, the measured output clock peak-to-peak jitter and rms jitter are 50ps and 10.6ps, respectively. The maximum lock time is 43 clock cycles at 150MHz.
In chapter 4, a fast-lock delay-locked loop for wide-range operation was proposed. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter scheme for phase range selector, a start-up circuit and coarse tune circuit to offer the faster locking time. And the multi-controlled delay cell for voltage-controlled delay line was used to provide wide locked range and the low-jitter performance. The charge pump circuit is implemented by digital controlled scheme to reach bandwidth tracking. The proposed DLL can solve the problem of the false locking associated with conventional DLL’s and wide-range operation. The circuit design and HSPICE simulation are based upon TSMC 0.25μm 1P5M N-well CMOS process with a 2.5V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 40 to 300 MHz. The maximum locking time is 22 clock cycles. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.
CHAPTER 1 Introduction......1
1. 1 Motivation......1
1.2 Thesis Overview......2
CHAPTER 2 The Characteristic of Delay-Locked Loop......3
2.1 Introduction......3
2.2 DLL Fundamentals......4
2.2.1 Phase Detector (PD)......5
2.2.2 Charge Pump (CP) /Loop Filter (LF)......8
2.2.3 Voltage-Controlled Delay Line (VCDL)......13
2.2.3.1 RC-Time-Constant Controlled Delay Cell......14
2.2.3.2 Current-Starved Controlled Delay Cell......15
2.2.3.3 Differential Symmetric Loads Delay Cell......15
2.3 Stability Analysis of DLL......17
2.4 Design Consideration of the Delay-Locked Loop......18
CHAPTER 3 Fast-Lock DLL with Power-On Reset Circuit......19
3.1 Introduction......19
3.2 The Locking Range Problem of Conventional DLL’s......20
3.2.1 Harmonic Locking......22
3.2.1 Stuck Locking......24
3.3 Architecture of The Proposed DLL with Power-On Reset Circuit......25
3.4 Circuits Description......27
3.4.1 Power-On Reset Circuit......27
3.4.2 Phase Detector (PD)......34
3.4.3 Charge Pump and Loop Filter......36
3.4.4 Coarse Tune Circuit......38
3.4.5 Delay Cell......41
3.5 Experiment Results......43
3.6 Conclusion......46
CHAPTER 4 Fast-Lock DLL for Wide-Range Operation......42
4.1 Introduction......42
4.2 Limited Range Problem of Conventional DLLs......45
4.3 Architecture and Operating Principle of The Proposed DLL...... 48
4.3.1 Phase Range Selector......51
4.3.2 Phase Detector......51
4.3.3 Start-up Circuit......53
4.3.4 Coarse Tune Circuit......53
4.3.5 Multi-Controlled Delay Cell......55
4.3.6 Digital Controlled Charge Pump and Loop Filter......58
4.4 Simulation and Comparison Results......60
4.5 Conclusion......64
CHAPTER 5 Conclusions and Future Works......65
REFERENCE ......67
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