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研究生:林家弘
研究生(外文):Chia-Hung Lin
論文名稱:高效率快速乘法器矽智產元件之測試策略
論文名稱(外文):An Efficient Test Strategy for Fast Multiplier Core
指導教授:饒建奇
指導教授(外文):Jiann-Chi Rau
學位類別:碩士
校院名稱:淡江大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:中文
論文頁數:65
中文關鍵詞:快速乘法器可測試性設計矽智產布斯演算法
外文關鍵詞:Fast MultiplierDesign for testabilityIntellectuall Property (IP)Booth''s algorithm
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對於以核心為基礎(Core-Based)所架構出來的系統晶片(System-on-a-Chip,SoC),要如何取得核心的測試向量是非常重要的一個步驟。軟體核心(Soft Cores)通常是以硬體描述語言的方式呈現出來,例如:VHDL或Verilog等。而要在較高階硬體描述語言中獲取測試向量要比從實際的邏輯電路上獲得更不容易。因此,本篇論文利用修正布斯演算法(Modified Booth’s Algorithm)並利用樹狀結構加法器作加總之乘法器架構設計出快速乘法器之軟體核心,可廣泛被使用於坎入式設計之系統晶片中。本研究論文是以矽智產(Intellectual Property,IP)提供者的角度來設計此軟體核心,所以在設計軟體核心時就先考慮到要如何測試,並且在必要時對整個快速乘法器架構加入可測試性設計,同時提供高效率的測試向量,而所提供之測試向量可經由模擬得知,可達到令人滿意的錯誤涵蓋率,使日後在測試時降低測試之成本與時間。
To test core-based SoCs, an important step is to get test sets for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test sets at higher level than at logic level. Tree structure summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex system on chip. From the viewpoint of core providers, the IP core designers not only employ design for testability (DFT) strategy for its cores, but also provide the most effective test sets for core users. In this paper, we propose a method to generate pseudo-exhaustive test patterns at function level. The proposed method can be used to generate test patterns for IP cores, especially, for soft IPs.
目錄
中文摘要 I
英文摘要 II
目錄 III
圖表目錄 VI
第一章 緒論 1
1.1 簡介 1
1.2 研究動機 4
1.3 論文架構 5
第二章 相關研究 7
2.1 簡介 7
2.2 循序式乘法器(Sequential Structure Multiplier) 8
2.3 陣列式乘法器(Array Structure Multiplier) 10
2.4 平行式乘法器(Parallel Multiplier) 12
2.4.1 部分乘積產生區塊(Partial Product Generation Block) 14
2.4.2 壓縮樹區塊(Compress Tree Block) 20
2.4.3 最終加法器區塊(Final Adder Block) 24
第三章 設計方式與硬體實現 29
3.1 簡介 29
3.2 部分乘積產生區塊(Partial Product Generation Block) 31
3.3 壓縮樹區塊(Compress Tree Block) 34
3.4 最終加法區塊(Final Adder Block) 40
第四章 測試策略 41
4.1 簡介 41
4.2 故障模型(Fault Model) 42
4.2.1 Cell Fault Model(CFM) 42
4.2.2 Cell Fault Coverage(CFC) 45
4.3 測試機制一 48
4.4 測試機制二 51
第五章 實驗結果 55
5.1 簡介 55
5.2 實驗方法 56
5.3 實驗數據 57
5.3.1 平行式乘法器之效能分析 57
5.3.2 平行式乘法器之故障涵蓋率分析 59
第六章 結論 61
參考文獻 62
附錄一 可合成之平行式乘法器Verilog HDL程式碼
附錄二 輔助電路合成之Script File
附錄三 BLIF Format描述之乘法器程式碼
參考文獻
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[2] Jalil Fadavi-Ardekani, “M × N Booth Encoded Multiplier Generator Using Optimized Wallace Trees,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 1 Issue: 2, Jun 1993, Page(s): 120 — 125
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[7] Wen-Chang Yeh, and Chein-Wei Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, Volume: 49 Issue: 7, Jul 2000, Page(s): 692 — 701
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[12] Dimitris Gizopoulos, Antonis Paschalis, and Yervant Zorian, “An Effective BIST Scheme for Booth Multipliers,” Internal Test Conference, 21 — 25 Oct 1995, Page(s): 824 — 833
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