最近，隨著可攜帶式通訊系統的普遍發展，低電壓極低功率消耗的電路系統已成為設計的趨勢。而積體電路內部採用多種電壓操作，以求得最佳化的操作速度與功率消耗。因此電荷幫浦常被應用於低電壓電路，作為昇壓轉換電路。而且電荷幫浦電路在快閃式記憶體和電子可擦拭記憶體的應用上，具有非常重要的地位，再寫入或抹除時，需要非常高的正電壓或負電壓。此外，電荷幫浦電路也被廣泛應用在切換電容式系統﹝如類比數位轉換器，或濾波器﹞。評估電荷幫浦電路效能最重要的是兩種導致電荷幫浦電路輸出電壓與效能降低的因素，即為場效電晶體的臨界電壓和基體效應。因此，將在本篇論文中提出兩個新型電荷幫浦電路，可以減少上述兩種因素所造成的影響。因此，面對第一個問題，基體效應所造成臨界電壓上升，本論文之電路設計上採用了Floating-well的架構，在此架構下，基體效應所造成臨界電壓上升 將會很小，原因是每顆採用Floating-well的P-型場效電晶體，其基極與源極的電壓差將一直維持在約一個臨界電壓，如此一來，P-型場效電晶體的源極與基極的電壓差將會維持在一固定值，P-型場效電晶體的臨界電壓就不會因為基體效應而逐級增高。第二個問題是臨界電壓的耗損，場效電晶體導通時，閘極與源極需要一個臨界電壓的電壓差，而此電壓差會造成電荷幫浦電路電壓增益的減少，本論文之電路則採用了Charge transfer switches的架構，來完全打開主要傳輸電荷的場效電晶體，使其充分的利用電容耦合效應，或將其關上，阻止逆電流產生，經由上述兩個架構，臨界電壓的耗損與基體效應對本論文之電路的輸出電壓增益的影響，與其他傳統電壓幫浦電路相比較，將被降到很低。在模擬比較上，我們首先比較了輸出電壓與電容級數的關係，輸出電壓與負載電流的比較，還有能源效率的比較。在晶片實作上，所得到的量測結果，在操作電壓為1V時，可以得到的輸出電壓為2.4V，此晶片可以正常工作。最後，將本論文所提出的CMOSCP應用在假靜態記憶體，由本電荷幫浦獲得高效能的電壓輸出，將高電壓應用於記憶胞的refresh，如此一來，能有效的將資料儲存在記憶胞，獲得高儲存密度。

Recently, low-voltage low-power integrated circuits are used in battery-power portable communication system. In such case, multi-level power supply designs could be considered as a compromise between speed and power dissipation. However, charge-pump circuit is used to generate a higher or lower supply voltage. It is well known that the charge-pump circuits play a very important role in Flash memory or EEPROM circuits. For example, programming or erasing the Flash memory cells needs very high positive and negative voltages. Those are also widely used in switched capacitor systems, such as A/D, D/A, and filter systems. The performance of the charge-pump circuits is evaluated by its charge-pump gain and energy transfer efficiency. In this thesis, two new charge-pump circuits are proposed. The major factors that will limit the charge-pump gain and efficiency are threshold voltage drop and body effect. The proposed new circuits can reduce such effects.In the first, the proposed positive charge-pump circuits use the charge transfer switches to eliminate the threshold voltage drop problems. The PMOS charge-pump circuit is added capacitances, which is smaller than the main capacitances, in the gate of the diode-connecting transistor. The added capacitances can keep the gate’s voltage of the PMOS transistor lower than its source and drain when requested. The CMOS charge-pump circuit is added the pair of MOS transistors, which can control the charge transfer switch scheme. The pair of MOS transistors can turn on and turn off the charge transfer switches completely when required. Second, the proposed positive charge-pump circuits use the floating well structure to eliminate the body effect problems. Due to these circuit schemes, The PMOS charge-pump circuit (PMOSCP) and the CMOS charge-pump circuit (CMOSCP) can be used in a conventional n-well CMOS process for low supply voltage (2V to 0.9V) and have high charge-pump gain and efficiency. The proposed circuit is based on the 0.25μm CMOS technology, and the clock frequency is 50MHz.Some simulation results are shown as follows. First, the simulation results of output voltage vs. number of capacitances, output voltage vs. output loading current, and energy efficiency. The simulation results compare with other conventional charge-pump circuits, and these are based on 0.25μm CMOS technology.The measurement result is shown. The optimal output voltage is about two times the input voltage when supply voltage is 1 volt. Furthermore, as shown in Figure 4.20, the saturation time of the Vout voltage is 12 microseconds and the output voltage is 2.4 volt when supply voltage is 1 volt.In this thesis, the CMOSCP circuit is applied to pseudo SRAM. The high output voltage of CMOSCP circuit is used to refresh the memory cell. Therefore, the pseudo SRAM can have high density.

CHAPTER 1 INTRODUCTION 1
1.1 Switched Capacitor System 1
1.2 Memory Circuits 4
1.3 Low Supply Voltage System 7
1.4 Thesis Organization 10
CHAPTER 2 REVIEWS OF CHARGE-PUMP CIRCUITS 11
2.1 Introduction 11
2.2 Dickson 11
2.3 NCP-X 13
2.3.1 NCP-1 13
2.3.2 NCP-2 15
2.3.3 NCP-3 16
2.3 The Moisiadis Charge-Pump Circuit 18
2.4 SP5 19
CHAPTER 3 THE NEW CHARGE-PUMP CIRCUITS 22
3.1 The Structure of the PMOS Charge-Pump Circuit 22
3.1.1 Floating well 23
3.1.2 Added smaller capacitances 23
3.1.3 Non-overlap clock signals 24
3.2 The Structure of the CMOS Charge-Pump Circuit 24
3.2.1 Floating well 25
3.2.2 Charge transfer switches 25
3.3 Performance Comparison and Simulation Results 26
3.3.1 Compare with other conventional charge-pump circuits 26
3.3.2 Compare with the threshold voltage 29
3.3.3 Loading capacitance vs. time 30
CHAPTER 4 CHIP IMPLEMENTATION AND COMPARISON RESULT 34
4.1 Introduction 34
4.2 Output Voltage vs. Number of Capacitances 34
4.3 Output Voltage vs. Output Loading Current 38
4.4 Energy Efficiency 41
4.5 Chip Implementation 44
4.5.1 The measurement result of CMOSCP circuit 45
CHAPTER 5 THE APPLICATIONS OF NEW CHARGE PUMP CIRCUIT 49
5.1 Introduction 49
5.2 2P2N Pseudo SRAM 51
5.2.1 2P2N cell 51
5.2.2 The column refresh structure 53
5.2.3 High voltage generator circuit 54
5.2.4 Refresh circuit 55
5.3 Simulate Results and Implementation 56
CHAPTER 6 CONCLUSION 60
REFERENCE 61

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