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研究生:吳建明
研究生(外文):Chien-Ming Wu
論文名稱:低面積通道解碼之積體電路架構研究
論文名稱(外文):Exploration of Area-Efficient VLSI Architecture for Channel Decoding
指導教授:黃穎聰黃穎聰引用關係吳建興吳建興引用關係
指導教授(外文):Ying-Tsung HwangChien-Hsing Wu
學位類別:博士
校院名稱:國立雲林科技大學
系所名稱:工程科技研究所博士班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2003
畢業學年度:91
語文別:英文
論文頁數:160
中文關鍵詞:有限場除法渦輪碼通道解碼超大型積體電路設計
外文關鍵詞:finite (Galois) field divisionturbo codesVLSI designchannel decoding
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隨著各類通信產品之應用需求與眾多研究人力的投入,數位通信技術的研究與相關硬體實現已成為半導體工業的明日之星,在此領域中,里德索羅門碼及迴旋碼為公認之有效率的錯誤更正碼,並已廣泛地應用在各種系統中,近幾年來由於渦輪碼的興起且其效能非常接近薛農極限,又為錯誤更正碼領域提供一個相當重要的研究主題。基於積體電路的發展與應用趨勢,本論文以降低硬體複雜度或/和高速電路實現為目標,研究與通道編/解器相關(包含有限場算數單元及渦輪解碼器)之積體電路(VLSI)架構設計。
首先我們基於J. Stein的演算法,延伸發展出三個應用於GF(2m) 之新遞迴式除法演算法:包含一遞迴收斂次數不超過2m-1次之基礎演算法,及兩個為簡化硬體複雜度而設計並可同時提高運算速度之改進演算法;透過心臟陣列式所實現之除法器電路不但具有低面積、高速的特性,同時也擁有高度的模組化及規則化,因此非常適合於VLSI實現。最後由比較結果說明,本論文所提出之除法電路無論在速度及面積上都比採用延伸Euclid演算法的除法電路好。
在渦輪碼方面,雖然它的解碼效能佳但其所採用的軟性輸入/軟性輸出解碼演算法之複雜度頗高,更吸引許多的學者投入探討渦輪碼的原理與如何簡化它的設計複雜度。本論文採用移動視窗 (Log-)MAP演算法推導出三種不同記憶體管理架構,並推演出一參數化的表示式來定義電路架構所需的記憶體、平均解碼速度及解碼潛藏期,這些表示式可應用於不同硬體架構的研發與設計。本論文同時利用上述成果完成一可應用於第三代行動通訊的解碼器,進一步分析不同參數對於面積/運算複雜度、記憶體功率消耗、解碼潛藏期及解碼速度的取捨。由於渦輪解碼器的應用廣泛,所發展的架構與提供的資訊兼具有研究與商業之雙重價值。
The demands on related communication products and the driving forces from many researchers have made the area of digital communications a very popular research topic. In this area, Reed-Solomon and convolutional codes are recognized as very powerful error-control codes and are widely used in many practical applications. Recently, with the performance being very close to the Shannon limit, the advent of turbo codes opens a new research domain and attracts much attention in past decade. In conjunction with the trend of integrated circuit technology and applications, this dissertation explores VLSI architectural design issues in channel coding, including both finite field arithmetic and turbo decoders, and aim at reducing the resultant hardware complexity and/or achieving high-speed implementations.
This research first carries out efficient modular division algorithms over GF(2m) by adopting a fundamental change at the algorithmic level. Based on the extended Stein’s algorithm, we have successfully proposed three novel division algorithms including (1) a basic prototype with guaranteed convergence in 2m-1 iterations and (2) its variants that lead to high-speed systolic designs as well as achieving low area-time complexity. This research also develops an area-efficient systolic circuit with lower area complexity of O(m). The developed low-complexity, high-speed modular division architectures feature highly modularity, regularity, and concurrency. Performance evaluation reveals that our systolic designs based on the extended Stein’s algorithm outperform the best design based on the extended Euclid’s algorithm by running about 80% faster and consuming less chip area.
The recently discovered turbo codes received tremendous attention because of their excellent error-correcting capability, but the underlying soft-input soft-output (SISO) decoding algorithms usually lead to highly complicated implementation. There have been many publications working on efficient implementations of SISO decoders; however, a systematic architectural study with cost/performance comparisons and complexity analysis is still not completed in the literature. In this dissertation, three general structures for efficient memory management of SISO decoders employing the sliding-window (Log-)MAP algorithm are developed and the associated mathematical representations are derived to evaluate the required memory size, average decoding rate, and latency based on the speed and the number of the adopted processors. The derived equations can be easily applied to construct a variety of VLSI architectures for different applications. Based on our development, a sliding-window Log-MAP decoder complying with the specification of third-generation mobile radio systems is realized to demonstrate the performance trade-offs among latency, average decoding rate, area/computation complexity, and memory power consumption. Due to the extensive usage of turbo decoders, it is obvious that results of this dissertation can be used as a basis of related research in the future and they are valuable and practical from both academic and industrial points of view.
中文摘要……………………………………………… i
英文摘要……………………………………………… ii
List of Figures……………………………………………… vii
List of Tables……………………………………………… x
Acknowledgements……………………………… xi
1. Introduction………………………………… 1
1.1 Overview………………………………… 1
1.2 Motivations and Results……………… 4
1.2.1 VLSI design of finite (Galois) field division…………………………………………… 4
1.2.2 Design and implementation of turbo decoders…………………………………………… 5
1.3 Outline of the Dissertation………… 8
2. High-Speed and Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2m)…………………………… 10
2.1 Introduction……………………………… 10
2.2 Extended Stein’s Algorithm for Division Over GF(p)…………………………… 14
2.3 Iterative Division Algorithm Over GF(2m)……………………………………………………… 16
2.3.1 Algorithm EBg………………………… 16
2.3.2 Algorithm EBd………………………… 18
2.3.3 Algorithm EBdf……………………… 18
2.3.4 Example………………………………… 20
2.4 Parallel I/O Systolic Array Implementations………………………………… 22
2.4.1 High-throughput VLSI design…… 22
2.4.2 Area-efficient design of EBd (AE-EBd)……………………………………………………… 28
2.5 Performance Evaluation……………… 30
2.6 Summary…………………………………… 34
3. Fundamentals and Iterative Decoding Algorithms of Turbo Codes ………………… 35
3.1 Introduction……………………………… 35
3.2 Why Turbo Codes………………………… 36
3.3 Turbo Encoder…………………………… 39
3.4 Interleaver……………………………… 43
3.5 Turbo Decoder (Iterative Decoder)… 46
3.6 Classes of Soft-Output Decoding Algorithms………………………………………… 48
3.6.1 Maximum a posteriori algorithm (MAP or BCJR algorithm)……………………………… 49
3.6.2 Max-Log-MAP algorithm and Log-MAP algorithm………………………………………… 59
3.6.3 Sliding window algorithm………… 62
3.6.4 Soft-output Viterbi algorithm (SOVA)………………………………………………………… 64
3.7 Summary……………………………………… 68
4. Performance and Structures of Turbo Codes………………………………………………… 70
4.1 Introduction……………………………… 70
4.2 Performance of Turbo Codes………… 71
4.2.1 The influence of the component decoding algorithms…………………………… 71
4.2.2 The influence of the number of iterations………………………………………… 72
4.2.3 The influence of the frame size… 73
4.2.4 The influence of the code rate… 74
4.2.5 The influence of the code generator polynomials………………………………………… 75
4.2.6 The influence of the specific design of the Interleaver……………………………… 76
4.3 Turbo Code Structures………………… 78
4.3.1 PCCC structures……………………… 78
4.3.2 SCCC structures……………………… 79
4.3.3 HCCC structures……………………… 82
4.4 Summary……………………………………… 85
5. Exploring General Memory Structures in SISO Decoders Using Sliding-Window (Log-)MAP Algorithm…………………………………………… 87
5.1 Introduction……………………………… 87
5.2 SW-(Log-)MAP Algorithm over D-Symbol Basis………………………………………………… 89
5.3 Memory Arrangement Based on SW-(Log-)MAP Algorithm overD-Symbol Basis………… 91
5.3.1 WAB arrangement……………………… 93
5.3.2 WAC arrangement……………………… 98
5.4 Examples and VLSI Realization……… 100
5.5 Performance Evaluation………………… 104
5.6 Summary……………………………………… 111
6. Design and Implementation of SW-Log-MAP Decoders…………………………………………… 112
6.1 Introduction……………………………… 112
6.2 Turbo Encoding Scheme in 3G Systems……………………………………………… 114
6.3 Architecture of SW-Log-MAP Decoder…116
6.4 Design and Implementation of Building Components………………………………………… 120
6.4.1 Branch metric calculator……………121
6.4.2 Forward processor…………………… 122
6.4.3 LLR (soft-output) calculator…… 126
6.4.4 Implementation loss………………… 128
6.5 Complexity and Performance Analysis…………………………………………… 129
6.6 Summary……………………………………… 134
7. Conclusions and Future Work………… 135
7.1 Conclusions………………………………… 135
7.2 Future Work………………………………… 138
Bibliography……………………………………… 139
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