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研究生:羅立狄
研究生(外文):Li-Dyi Luo
論文名稱:基於半葛雷碼的低電壓互補金氧半快閃式類比對數位轉換器之設計
論文名稱(外文):Design of Low-Voltage CMOS Flash Analog-to-Digital Converter Based on Half-Gray Code
指導教授:李蒼松
指導教授(外文):Tsung-Sum Lee
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子與資訊工程研究所碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:91
語文別:中文
論文頁數:65
中文關鍵詞:互補金氧半低功率低電壓完全快閃式類比對數位轉換器
外文關鍵詞:CMOS、Low-Power、Low-Voltage、Full-Flash Analog-
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互補金氧半8Bit,33.3Ms/s快閃式類比對數位轉換器用在正負1.5伏的電源電壓己經被發展,經由使用一個低功率高速互補金氧半全差動比較器。在容易產生雜訊的數位電路,達到好的訊號對雜訊及失真比。類比對數位轉換器的架構是以全差動的形式。差動非線性的錯誤,低於 0.3LSB。在取樣頻率是在33.3MS/s而且輸入頻率是在4MHz得到信號對雜訊比為46.2dB。在33.3MS/s用3V的電源電壓消耗功率為106mW。
A CMOS 8-bit, 33.3Ms/s flash ADC with 1.5V power supply is developed through the use of a low-power high-speed CMOS fully differential comparator. To achieve good signal-to-(noise and distortion) ratio in the presence of noisy digital circuitry, the architecture of the ADC is fully differential. The differential nonlinearity error in dynamical operation is less than 0.3LSB. Signal-to-noise ratio is 46.2dB at a sampling rate of 33.3MS/s and input frequency of 4MHz. The power dissipation is 106mW at 33.3MS/s with 3V power supply.
中文摘要 -------------------------------------------------- i
英文摘要 -------------------------------------------------- ii
誌謝 -------------------------------------------------- iii
目錄 -------------------------------------------------- iv
表目錄 -------------------------------------------------- vi
圖目錄 -------------------------------------------------- vii
第一章 緒論 1
1.1 研究動機------------------------------------------ 1
1.2 研究目標------------------------------------------ 2
第二章 類比對數位轉換器之基本概念 3
2.1 何謂A/D? ---------------------------------------- 3
2.2 A/D轉換器種類之簡介------------------------------ 4
2.3 描述A/D轉換器特性參數---------------------------- 6
2.4 設計A/D Converter的基本理論----------------------- 10
2.4.1 奈奎氏取樣率-------------------------------------- 10
2.4.2 量化誤差(Quantization errors)所產的SNDR和ENOB值--- 10
第三章 快閃式類比數位轉換器設計之考量 13
3.1 CMOS開關---------------------------------------- 13
3.1.1 開關導通電阻-------------------------------------- 13
3.1.2 時脈滲入------------------------------------------ 14
3.1.3 電荷注入效應-------------------------------------- 15
3.2 參考電路的非線性考量------------------------------ 17
3.3 影響轉換速度因素之探討---------------------------- 19
第四章 快閃式類比對數位轉換器之電路解析 23
4.1 A/D Converter電路架構------------------------------ 23
4.2 比較器的探討-------------------------------------- 24
4.2.1 全差動放大器之原理解析---------------------------- 26
4.2.2 反相器之原理-------------------------------------- 28
4.2.3 Latch電路設計------------------------------------- 30
4.2.4 全差動比較器之抵補電壓消除方程式------------------ 30
4.3 D-FF 閂鎖(Latch)電路------------------------------- 32
4.4 完成的偵測電路------------------------------------ 33
4.5 One of all的編碼的產生------------------------------ 34
4.6 格雷碼的可邏輯陣列編碼矩陣------------------------ 35
4.6.1 不穩定(Metastability)的影響-------------------------- 35
4.6.2 不穩定(Metastability)的改善方式---------------------- 35
4.7 半葛雷碼碥碼器縮短延遲時間------------------------ 38
第五章 電路的模擬方法與結果 39
5.1 比較器的輸出放大曲線------------------------------ 39
5.2 比較器的模擬方法與結果---------------------------- 39
5.3 A/D轉換器測試動態性能的方法---------------------- 42
5.3.1 FFT測試方法與結果-------------------------------- 42
5.3.2 Histogram 測試方法結果---------------------------- 44
5.3.3 PSRR之測試方法----------------------------------- 47
5.3.4 取樣頻率與動態消耗功率之關係---------------------- 47
5.3.5 放大器電流消耗對延遟時間之關係-------------------- 48
5.4 經過實際佈局後模擬之結果:------------------------- 49
第六章 電路之佈局情形 54
6.1 佈局的考量---------------------------------------- 54
6.2 類比元件之佈局考量-------------------------------- 56
6.3 快閃式A/D轉換器實際佈局的計劃-------------------- 57
第七章 結論 60
7.1 總結---------------------------------------------- 60
7.2 未來方向------------------------------------------ 60
參考文獻 61
附錄一 指導教授發表相關論文 63
附錄二 MOS電晶體之通道長寬值大小 64
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