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研究生:崔志強
論文名稱:動態調整式低功率快取記憶體架構
論文名稱(外文):Adaptive way configurable architecture for low power cache
指導教授:陳添福陳添福引用關係
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:46
中文關鍵詞:互補式電路集合式聯結動態模式控制動態路組態
外文關鍵詞:CMOS circuitset-associativeAdaptive mode controlAdaptive way configuration
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為了增進電腦處理器的效能,我們不但增加電腦處理器的快取記憶體容量的大小,並且也增加快取記憶體的集合式聯結(set-associative)。可是這樣子會增加整體的電流消耗。當可攜式裝置越來越發達的時候,電流消耗就成了設計電腦處理器的一個重要考量。互補式電路(CMOS circuit)的電流消耗主要分為靜態電流消耗跟動態電流消耗。而近幾年,靜態電流的消耗變的越來越重要,所有也有部分的研究開始在降低靜態電流的消耗。其中有個動態模式控制(Adaptive mode control)的快取記憶體架構是目前所知在降低靜態電流消耗的同時也可以兼顧到維持高效能。但是在0.13um的製程下,動態電流還是佔著L1快取記憶體主要的耗電。
  
  在這一篇論文中,我們提出一種節省動態電流消耗的方法。我們將該方法附加在動態模式控制的快取記憶體架構上面。稱之為動態路組態(Adaptive way configuration)快取記憶體。當要存取快取記憶體的時候,我們利用預先存好的資訊來得知這次存取的快取記憶體集合是哪種集合式聯結。這預先存好的資訊可以讓我們知道我們這次是存取四路還是兩路。我們也會利用被關掉的快取記憶體區塊的資訊來知道還有哪路是不需要被使用的。我們降低被使用的路的個數來達到節省動態電流消耗。經由實驗模擬的結果,我們所提出的方法可以有效節省動態電流的消耗。

Microprocessor performance has been improved by increasing not only the size of on-chip caches but also the way set-associative of on-chip caches. However, that increases the total power consumption. When the increasing of use of portable computing systems. Power consumption also becomes an important design consideration for microprocessor. Static power consumption becomes more and more important. So the recent year, some researches begin focus on static power reduction. One of those researches is AMC cache. AMC cache is the better method of the present researches, because AMC cache reduces static power consumption while maintaining high performance. But dynamic power consumption still dominates the L1 cache power consumption for a 0.13um technology.
In this paper, we present our method to reduce dynamic power consumption. We attach our method on AMC cache. We name our method as adaptive way configuration cache (AWC cache). When a cache access occurs, we use pre-stored information of the cache set to know the set-associative of the cache set. The pre-stored information can let us know that we need to access four ways or only two ways. We also use cache block turn off information to know which way does not need to be used. We reduce the number of active ways on each cache access, so we can save dynamic power consumption. Simulation results show that our method can efficient save dynamic power consumption.

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Main Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Related Work 4
2.1 Cache Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Lower Power Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Reduce Activated Ways for Dynamic Power Reduction . . . . . . . . 5
2.2.2 Reduce Alive Cache Block for Static Power Reduction . . . . . . . . . 8
3 Adaptive Way Configuration Architecture 12
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Key idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Tag Permutation Status & Configuration Register . . . . . . . . . . . 17
3.3.2 Configuration Decider Unit . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3 Configuration Function Unit . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.4 CDU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Experiment Results 30
4.1 Experiment Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Additional Hardware Delay of AWC . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.1 Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Instruction Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.3 Data Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5 Conclusion 42

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