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研究生:黃麟傑
研究生(外文):Lin-Chieh Huang
論文名稱:低功率MPEG-1/2/4移動補償數位矽智財核心之設計與實作
論文名稱(外文):Low-Power Design and Implement of the Multi-MPEG Motion Compensation IP Core
指導教授:郭 峻 因
指導教授(外文):Jiun-In Guo
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2004
畢業學年度:92
語文別:英文
論文頁數:82
中文關鍵詞:移動補償非整數像素內插計算移動向量移動向量預測
外文關鍵詞:Motion compensationfractional-pixel interpolationMotion vectorMV predict
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移動補償技術為現今多媒體影像壓縮技術中核心技術的一種,其主要的功能是利用降低Temporal redundancy以達到較高的壓縮比例,由於連續影像中的資料相似性極高,因此使用移動補償技術可以達到極高的影像壓縮比,因此在許多的影像壓縮標準裡皆被採用,如MPEG-1、MPEG-2、MPEG-4以及H.26x等。由於移動補償技術經常伴隨著大量的像素內插計算,因此移動補償模組亦為影像解碼器中最具計算量的單元之一。由於「高畫質影像(DTV、HDTV)之即時解碼」,以及「應用於可攜式裝置之低功率設計」之需求,對於影像的解碼器系統而言,具備一種具有高效能且低功率之移動補償模組顯的相當重要。
本論文之題綱為「低功率MPEG-1/2/4移動補償數位矽智財核心之設計與實作」,主要論述移動補償在MPEG-1/2/4影像解碼器之低功率設計,主要的方法包含了:『FIFO-based MV predictor』,『Adder-based interpolator』以及『Dynamic Partial Guarded Computation Interpolator (DPGCI)』以達到移動補償模組低功率之設計。FIFO-based MV predictor 利用MPEG-4移動向量預測方法之特性,使用FIFO來儲存移動向量,可達到節省記憶體空間及節省硬體成本之效果。 Adder-based interpolator 技術中,利用了interpolator中係數之特性,以加法器取代大量乘法器來進行內插計算,可節省較多的硬體資源並提高內插計算之效能。 DPGCI技術主要的精神是先將資料在運算前進行分析,動態地將電路劃分為須運算與無須運算兩部分,並且將無須運算之部分電路凍結,如此可以達到節省約60%運算之功率消耗。
為確保本設計之正確性,我們分別在不同的層次進行系統之驗證,包含了Behavior functional驗證、RTL驗證、Gate level驗證,以及FPGA的prototyping驗證,並且採用了Synopsys Formality tool 以確保RTL與Gate level之相等性。本設計採用UMC 0.18 μm CMOS technology,最高可工作在125 MHz工作頻率下,並且可支援HDTV1080i 視訊解碼之高效能的需求。本設計可降低約60%內插計算之功率消耗(使用NANOSIM 功率分析工具)。此外,為了使本設計能符合IP設計之品質要求,所有RTL Code皆經過 NOVAS nLint 工具進行 Coding Check 以確定沒有錯誤產生;而在 Testing Code coverage部分,我們採用了ModelSim Code Coverage tool 來檢視測試檔案是否完整,結果顯示本設計之測試度達100%。
最後我們將所提設計成功地整合進MPEG-4 Video Decoder系統IP中,並於Xilinx Multimedia board上完成FPGA prototyping之驗證,在系統工作頻率於27 MHz下可進行MPEG-4 CIF Video之即時解碼。

Motion compensation is one of the core techniques for video compression in many multimedia applications. This technique is taken by several well-known video compression standards, such as MPEG-1, MPEG-2, MPEG-4, and H.26x. Motion compensation is popularly used for reducing the temporal redundancy to enhance the compression ratio. Owing to the huge computations performed by fractional-pixel interpolation, the processing time and power consumption of motion compensation become one of the major computing parts for a video decoder system. For high image quality requirements (such as HDTV) and low-power requirements in portable application in mobile devices, a high performance and low power consumption motion compensation design is more and more demanding for current video decoder systems.
This thesis concentrates on low-power Motion Compensation (MC) design for the Multi-MPEG (MPEG-1/2/4) video decoder. The proposed design approaches include a FIFO-based MV predictor, an Adder-based interpolator for low cost consideration, and a Dynamic Partial Guarded Computation Interpolator (DPGCI) technique that divides the operation into needed-compute part and unneeded-compute part and freeze the unneeded-compute part to achieve the low-power dissipation target. This thesis not only presents the MC IP core design, but also discusses MC design on processors to accelerate the MC operation of video decoding on general proposed processors.
To ensure the validity of the proposed MC design, we verify the proposed design in several different levels such as Behavior functional verification, RTL verification, gate level verification, and FPGA verification. Besides, we use Synopsys Formality tool to compare the equivalence between RTL and gate level. The proposed design uses UMC 0.18 µm CMOS technology. In addition, the power consumption of interpolation operation in the proposed design is reduced from 60.3538 µW to 18.3863 µW when operating at 54 MHz under 1.8V supply voltage. The saving power-consumption is more than 60% by using NANOSIM measurement on the netlist level. To keep the quality of the proposed design, it has been qualified through RTL coding check by NOVAS nLint and coverage check by ModelSim Code Coverage tool in terms of 100% code coverage.
Finally, the proposed design has been integrated into a MPEG-4 video decoder IP that has been verified in the Xilinx multimedia board. The FPGA prototyping could achieve the MPEG-4 CIF video real-time decoding when operated at 27 MHz.

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Background and Motivation . . . . . . . . . . . . . . . 2
1.1.1 Background . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Scope of the Thesis . . . . . . . . . . . . . . . . . . 4
2 Previous Work . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Motion Compensation . . . . . . . . . . . . . . . . . . 6
2.2 Fractional Pixel Interpolator Design . . . . . . . . . . 10
2.2.1 Half-pixel Interpolation . . . . . . . . . . . . . . . 10
2.2.2 Quarter-pixel Filtering . . . . . . . . . . . . . . . 12
2.3 Low Power Design . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Partially Guarded Computation . . . . . . . . . . . . 14
3 Algorithm Derivation . . . . . . . . . . . . . . . . . . . 18
3.1 Half-pixel Interpolation Algorithm . . . . . . . . . . . 18
3.2 Quarter-pixel Filtering Algorithm . . . . . . . . . . . 19
3.2.1 Calculation of the half sample values . . . . . . . . 20
3.2.2 Calculation of the quarter sample values . . . . . . . 21
3.3 DPGC Algorithm . . . . . . . . . . . . . . . . . . . . . 21
4 Architecture Design . . . . . . . . . . . . . . . . . . . 26
4.1 Multi-MPEG MC Architecture . . . . . . . . . . . . . . . 26
4.2 Motion Vector Predictor . . . . . . . . . . . . . . . . 30
4.3 Half-pixel Interpolator . . . . . . . . . . . . . . . . 32
4.4 Quarter-pixel Filter . . . . . . . . . . . . . . . . . . 33
4.5 DPGC Based Interpolator . . . . . . . . . . . . . . . . 39
5 IP Realization . . . . . . . . . . . . . . . . . . . . . . 43
5.1 IP Design Flow . . . . . . . . . . . . . . . . . . . . . 43
5.2 Functions and Features of IP . . . . . . . . . . . . . . 46
5.3 IP Verification . . . . . . . . . . . . . . . . . . . . 47
6 Motion Compensation Realization on Processors . . . . . . 50
6.1 DataPath Design . . . . . . . . . . . . . . . . . . . . 51
6.2 Firmware Library . . . . . . . . . . . . . . . . . . . . 54
6.3 Verification Strategy . . . . . . . . . . . . . . . . . 56
7 Simulation and Performance Analysis . . . . . . . . . . . 58
7.1 MC IP Design . . . . . . . . . . . . . . . . . . . . . . 58
7.1.1 Simulation Results . . . . . . . . . . . . . . . . . . 58
7.1.2 Synthesis Results . . . . . . . . . . . . . . . . . . 59
7.1.3 Comparisons . . . . . . . . . . . . . . . . . . . . . 60
7.2 MC Realization on Processors . . . . . . . . . . . . . . 61
7.2.1 Simulation Results . . . . . . . . . . . . . . . . . . 61
7.2.2 Synthesis Results . . . . . . . . . . . . . . . . . . 62
7.2.3 Comparisons . . . . . . . . . . . . . . . . . . . . . 62
8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 63
8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 63

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