臺灣博碩士論文加值系統

本論文使用TSMC 0.18μm CMOS製程以研製“應用於生理檢測訊號系統之2.4GHz CMOS射頻接收機”。在接收機的規劃上，為因應生理檢測系統之需要，著重於低雜訊與低功率消耗之特點，並將射頻訊號應用於2.4GHz之ISM頻帶，所設計之電路有：低雜訊放大器(LNA)、混頻器(mixer)、壓控振盪器(VCO)、及發收切換開關(T/R switch)等。
2.4GHz可調開關式壓控振盪器，其量測結果為：輸出頻率2.05~2.39GHz、相位雜訊-90.1dBc/Hz@1MHz、調諧範圍為340MHz、輸出訊號功率-4.83dBm、功率消耗7.5mW。2.4GHz CMOS發收切換開關，量測時以發射與接收兩模式進行，其量測結果分別為：發射模式時，發射端之返回損耗-19.8dB、插入損耗-2.17dB、隔離度-45.8dB、1dB增益壓縮點13dBm；接收模式時，接收端之返回損耗-22.7dB、插入損耗-1.98dB、隔離度-29dB、1dB增益壓縮點12dBm。2.4GHz低功率消耗之混頻器疊接低雜訊放大器，其模擬結果為：轉換增益20.55dB、雜訊指數3.517dB、功率消耗13.4mW、LO至IF隔離度-87.9 dB、RF至IF隔離度-112.9 dB、1dB增益壓縮點-25dBm、三階截斷點-16.5dBm。所有電路模擬均使用安捷倫之Advanced Design System(ADS)設計完成。

This thesis presents the development of CMOS RFICs for “2.4GHz CMOS RF Receiver for Medical Diagnosis Application” with TSMC 0.18μm CMOS process. For the demands of medical diagnosis application, the CMOS RF receiver is focused on low power consumption and low noise, and operated at 2.4GHz ISM band. The CMOS RFICs include LNA, mixer, VCO, and T/R switch.
The switched tuning VCO operates around 2.05GHz to 2.39GHz with —90.1dBc/Hz@1MHz phase noise, tuning range of 340MHz, output power of —4.83dBm, and power consumption of 7.5mW. The 2.4GHz T/R switch was measured in transmission and reception modes, respectively. In transmission mode, the measured results are return loss of -19.8dB, insertion loss of -2.17dB, isolation of -45.8dB, and P1dB of 13dBm. In reception mode, the measured results are return loss of -22.7dB, insertion loss of -1.98dB, isolation of -29dB, and P1dB of 12dBm. The low power LNA/mixer topology shows the mixer stacked on top of the LNA. The total DC power consumption is just 13.4mW with a supply of 7.4mA and 1.8V. The simulated performances of the topology are conversion gain of 20.5dBm, noise figure of 3.6dB, power consumption of 13.4mW, LO to IF isolation of —87.9dB, RF to IF isolation of —112dB, P1dB of —25dBm, and IIP3 of —16.5dBm. All circuits were designed and simulated by Advanced Design System (ADS).

第一章 緒論
1.1 簡介
1.2 論文接收機架構簡介
第二章 CMOS射頻前端接收機系統架構
2.1 簡介
2.2 超外差接收機
2.3 直接降頻接收機
2.4 雙降頻式接收機
2.5 接收機效能參數
2.5.1 雜訊指數
2.5.2 交互調變失真
2.5.3 1dB增益壓縮點
第三章 2.4GHz CMOS低雜訊放大器與混頻器
3.1 簡介
3.2 CMOS低雜訊放大器
3.2.1 CMOS低雜訊放大器基本架構
3.2.2 CMOS低雜訊放大器雜訊模型推導
3.3 CMOS電流共用低雜訊放大器
3.4 2.4GHz CMOS電流共用低雜訊放大器之模擬結果
3.5 CMOS混頻器
3.6 CMOS電流抽出混頻器
3.7 2.4GHz CMOS電流抽出混頻器之模擬結果
3.8 2.4GHz低功率消耗之混波器疊接低雜訊放大器
3.9 2.4GHz低功率消耗之混波器疊接低雜訊放大器之模擬結果
3.10 結果與討論
第四章 2.4GHz CMOS壓控振盪器
4.1 簡介
4.2 振盪器基本原理
4.2.1 CMOS L-C振盪器原理
4.2.2 相位雜訊
4.3 可調開關式壓控振盪器
4.4 運用解碼器選擇可調開關式壓控振盪器
4.5 2.4GHz CMOS壓控振盪器之模擬結果
4.6 2.4GHz CMOS壓控振盪器之量測結果
4.7 結果與討論
第五章 2.4GHz CMOS發收切換開關
5.1 簡介
5.2 CMOS T/R Switch基本原理
5.3 2.4GHz CMOS T/R Switch
5.4 2.4GHz CMOS T/R Switch之模擬結果
5.5 2.4GHz CMOS T/R Switch之量測結果
5.6 結果與討論
第六章 結論與未來發展
6.1 結論
6.2 未來發展
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