臺灣博碩士論文加值系統

隨著CMOS電晶體通道長度的縮小，設計出一個低價、低功率、高整合性的晶片已成為一種趨勢。所以，本論文是以 TSMC 0.18μm 1P6M CMOS 製程的RF model 來設計2.4GHz 射頻前端接收機。本研究包含一整合收發開關及主動分波器之2.4GHz可調增益低雜訊放大器和一混波器。此前端電路使用了低中頻架構來得到高積體化及低功率消耗。在本論文當中的低雜訊放大器，使用了一種較新的技術，使得再調整增益變化的時候，不至於影響增益平坦度與輸入輸出的阻抗匹配。這個低雜訊放大的的另一個特性，像一個主動Balun一樣，可以將單端輸入訊號轉為雙端訊號輸出。在特性的部分，整合收發開關及主動分波器之2.4GHz可調增益低雜訊放大器可以提供高增益19.15 dB、雜訊指數1.8 dB、增益可調範圍約為12 dB和三階截斷點為2 dB；混波器提供轉換增益7.06 dB和三階截斷點為-6.5 dBm。

With the scaling down of CMOS technology, it has become a new trend to design a CMOS IC with low cost, low power and high integration. Therefore, in this thesis, we describe the design of front-end chipset for a 2.4GHz RF receiver, which was fabricated by a TSMC 0.18 μm 1p6m CMOS process. The inplemented chipset includes a single-pole, double-throw transmit/receive switch (T/R switch), variable gain low-noise amplifier (LNA) with active differential-phase splitters and mixer. The front-end receiver uses a low-IF architecture for high level of integration and low power consumption. A novel gain control technique is proposed which does not affect the matching at the input and the output ports, as well as gain flatness of the LNA when the gain is varied. Another feature of this LNA is that it also acts as an active balun for converting the single-ended input to a differential output. The integration of a 2.4GHz T/R switch and variable gain LNA with on-chip active balun provides a gain of 19.2 dB, noise figure of 1.8 dB, gain variation of 12 dB and an IIP3 of 2 dB. The mixer provides conversion gain of 7.06 dB and IIP3 of -6.5 dBm.

中文摘要..............................................I
英文摘要.............................................II
致謝................................................III
目錄.................................................IV
第一章 緒論
1.1 前言.........................................1
1.2 研究目的與方法...............................3
第二章 CMOS接收機之系統架構與分析
2.1 一般觀念.....................................5
2.1.1 接收機與發射機之基本功能.....................5
2.1.2 交互調變與電路線性度.........................6
2.2 超外差式接收機...............................8
2.2.1 鏡像頻率....................................10
2.2.2 靈敏度......................................12
2.2.3 選擇性......................................13
2.2.4 半中頻的影響................................15
2.3 直接降頻式接收器架構........................16
2.3.1 直流位準偏移................................17
2.3.2 偶次諧波之真................................18
2.3.3 同相/正交相的不匹配.........................19
2.3.4 顫動雜訊....................................20
2.4 低中頻接收器架構............................21
第三章 接收機之重要規格
3.1 反射係數....................................22
3.2 增益........................................22
3.3 隔離度......................................23
3.4 雜訊指數....................................24
3.5 穩定度......................................26
3.6 交互調變失真................................27
3.7 1dB抑制點...................................28
3.8 三階截斷點..................................29
第四章 RFIC設計考量
4.1 RFIC設計流程................................32
4.2 元件模型與電路設計的關係....................33
4.2.1 NMOS電晶體..................................33
4.2.2 MIM電容.....................................34
4.2.3 螺旋式電感..................................35
4.3 Bond-wire 及 Pad............................36
第五章 整合收發開關及主動分波器之2.4GHz可調
增益低雜訊放大器
5.1 簡介........................................38
5.2 CMOS低雜訊放大器原理........................39
5.2.1 低雜訊放大器基本架構........................39
5.2.2 雜訊模型推導................................42
5.3 CMOS收發切換開關設計概論....................45
5.3.1 收發切換開關簡介............................45
5.3.2 收發切換開關基本架構........................45
5.4 整合收發開關及主動分波器之可調增益
低雜訊放大器之設計..........................48
5.4.1 電路架構與分析..............................48
5.4.2 設計流程....................................54
5.4.3 模擬結果....................................55
5.4.4 量測考量....................................64
5.4.5 晶片佈局平面圖..............................65
第六章 2.4GHz CMOS混波器
6.1 簡介........................................67
6.2 CMOS混波器原理..............................68
6.2.1 非線性式混波器..............................68
6.2.2 乘法器式混波器..............................72
6.3 2.4GHz CMOS混波器之設計.....................76
6.3.1 電路架構與分析..............................76
6.3.2 設計流程....................................78
6.3.3 模擬結果....................................78
6.3.4 量測考量....................................85
6.3.5 晶片佈局平面圖..............................87
第七章 結論與未來發展
7.1 結論........................................88
7.2 未來發展....................................89
參考文獻.............................................90

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