臺灣博碩士論文加值系統

本研究提出以階層式的設計方法實現應用於心電圖信號監測系統之微功率類比信號處理器單晶片。對於高效能類比信號處理器設計所面臨的關鍵性問題，包括偏移電壓的降低、雜訊的性能、功率的消耗、以及取決於製程的限制，亦有進一步的分析與研究。以自行設計的高效能運算放大器為基礎，成功的開發出建構類比信號處理器所需的電路；包含了儀器放大器，增益放大器和開關電容低通濾波器。
本論文探討了一些電路設計的技術，用於改善類比信號處理器的效能。以自動歸零技巧為基礎，配合兩階段20 kHz驅動時脈的動態偏移電壓消去技術用來改善儀器放大器的非理想偏移電壓和低頻雜訊。利用中度反轉區偏壓技術設計運算放大器，以減小電路的功率消耗。寬幅疊接的電路架構用來改善VT 參考偏壓電路以提供類比信號處理器更精確的偏壓電流。分析結果顯示寬幅疊接的偏壓技術可以使運算放大器偏壓點設計受到製程變化的影響大幅降低。
類比信號處理器每一個子電路設計均以level-49 SPICE模型進行模擬。所有電路的性能皆以開發的測試晶片加以驗證。晶片的製作採用0.5 μm、雙層複晶矽雙層金屬之互補式金氧半電晶體製程，晶片面積僅有0.52 mm2。實驗結果證明以自動歸零技巧為基礎的動態偏移電壓消去技術所設計之儀器放大器可以實現低於180 μV的輸入偏移電壓和小於0.67 μVRMS的等效均方根輸入雜訊。
類比信號處理器積體電路可以操作於3.3至5伏特範圍的單電源電壓。工作於3.3伏特與5伏特電源電壓時，分別消耗了0.39 mW與0.75 mW的功率。處理器晶片工作於5伏特之電源電壓時，其等效均方根輸入雜訊為6.3 μVRMS，等效輸入偏移電壓為 –0.87 mV，且頻寬大於100 Hz。利用寬幅疊接的設計技術，在直流的狀況下可以得到非常高的共模拒斥比以及非常高的電源拒斥比。IC驗證結果顯示所有量測參數皆可符合設計時的規格需求。
任意波形產生器用來模擬輸入心電圖信號以進行IC功能的驗證。實驗證明類比信號處理器可以滿足心電圖信號監測系統應用的需求。由於具有低雜訊、低偏移電壓、低功率消耗以及晶片面積很小的優點，使得本論文所提出的類比信號處理器積體電路非常適用於心電圖信號處理。

This study devises a hierarchical design methodology for a micro power analog processor single-chip realization and its ECG-monitoring system applications. Critical issues relating to the design of a high-performance analog processor, including offset minimization, noise performance, power consumption and process-dependent limitations, are investigated. Based on the proposed high-performance operational amplifier, all building blocks of the processor IC are constructed successfully, including an instrumentation amplifier, gain amplifier and switched-capacitor low pass filter.
Design techniques are explored to enhance the circuit performance of the analog processor IC. The non-ideal offset voltage and the low-frequency noise of the instrumentation amplifier are improved using an autozero-based dynamic offset-cancellation technique involving a two-phase clocking scheme with a frequency of 20 kHz. Power dissipation is minimized using the moderate-inversion biasing operational amplifier design. The improvement of the VT reference bias circuit using the wide-swing cascode architecture provides a more accurate current for the processor IC. The analytical results demonstrate that the proposed reference generator can minimize the dependence of the operating points of operational amplifiers on process variations.
Computer simulation has been undertaken using the level-49 SPICE model for every module design of the processor IC. A test chip was developed to examine the design performance using a 0.5-�慆 double-poly double-metal CMOS technology, and has a size of just 0.52 mm2. Experimental outcomes prove that the instrumentation amplifier realizes a low input offset voltage of less than 180 μV and an equivalent RMS input noise maximum of 0.67 using the autozero-based dynamic offset-cancellation technique.
The analog processor IC can be operated at single supply voltage ranging between 3.3 and 5 Volts, and achieves low power consumption of 0.39 mW and 0.75 mW at supply voltages of 3.3 V and 5 V, respectively. This chip has an equivalent RMS input noise of 6.3 , a typical equivalent input offset voltage of –0.87 mV, and a bandwidth exceeding 100 Hz at a supply voltage of 5 V. A high common-mode rejection ratio and a high power-supply rejection ratio at DC are attained using the wide-swing cascode architecture. IC verification reveals that the analog processor meets the design specifications.
The functions of the proposed IC have been identified using the simulated input ECG signal. Experimental results demonstrate that this processor IC is appropriate for the ECG-monitoring system applications. The advantages of low noise, low offset, low power dissipation, and minimum chip size make the analog processor IC suitable for ECG signal processing.

Chapter 1 Introduction
1.1 Background and Motivation 1-1
1.2 Research Goals 1-8
1.3 Thesis Organization 1-8

Chapter 2 Critical Issues Concerning the Design of a High- Performance Analog Processor
2.1 Noise 2-1
2.2 Offset 2-4
2.3 Process-Dependent Limitation 2-5
2.4 Power Dissipation 2-7
2-5 IC Specifications 2-8
2-6 Design Considerations 2-12

Chapter 3 Design Approach and Circuit Implementation
3.1 Accurate Biasing 3-1
3.2 High-Performance Operational Amplifier Design 3-9
3.3 Autozero-Based Offset Compensation Scheme 3-27
3.4 Core Circuit Implementation 3-41
3.5 Test Chip Development 3-54

Chapter 4 Experimental Results
4.1 Testing Configuration 4-1
4.2 Performance Parameters 4-3
4.2.1 1/f Noise 4-3
4.2.2 Offset Voltage and DC Gain 4-10
4.2.3 Power Consumption 4-19
4.3 Function Verification 4-22
4.4 Discussion 4-33

Chapter 5 Conclusions and Future Works
5.1 Conclusions 5-1
5.2 Future Works 5-3

References

List of Illustrations
Fig. 1-1. Simplified block diagrams of a patient-monitoring system….………...1-3
Fig. 2-1. The schematic model of an electrode interface for ECG measurement..2-2
Fig. 2.2. Functional block diagrams of the proposed analog processor IC…….2-8
Fig 2-3. Typical circuit block diagrams for use in monitoring ECG signal….....2-11
Fig. 3-1. A conventional self-biased VT-reference circuit…………………..…...3-2
Fig. 3-2. Improved wide-swing cascode VT-reference circuit……………..…….3-4
Fig. 3-3. Comparison of error current between the conventional VT reference and the improved wide-swing cascode bias circuit with different error voltageΔVE….……………………………………….……………………….3-5
Fig. 3-4. Relationship between the bias current and the parameter “n” in the bias circuit design…………………………………….……………………..3-6
Fig. 3-5. Symmetrical layout of all BJTs in the bias circuit…………………....3-7
Fig. 3-6. Layout cross-section of a BJT in P-substrate CMOS technology……...3-8
Fig. 3-7. Schematic diagram of the two-stage rail-to-rail input/output OP……...3-9
Fig. 3-8. Parameters for calculating Vgs and Ids in the moderate inversion region………………………………………………………………...3-13
Fig. 3-9. Comparison between the simulated and measured drain current Id. The gate voltage of 1 V, 1.5 V and 2 V are applied to the test NMOS transistor.……………………………………………………………..3-14
Fig. 3-10. Comparison between the simulated and measured drain current Id in the weak-inversion region. A 0.5-V gate voltage is applied to the test NMOS transistor……………………………………..……………………….3-15
Fig. 3-11. Simulated static current of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively.……………………………………..……3-21
Fig. 3-12. Simulated gain of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively………………………………….……………….3-22
Fig. 3-13. Simulated phase margin of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively……………………………….…..………3-23
Fig. 3-14. Simulated CMRR of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively………………………………………………3-24
Fig. 3-15. Simulated PSRR+ of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively………………………………………………3-25
Fig. 3-16. Simulated PSRR– of the designed OP at the supply voltages of (a) 3 V, and (b) 5 V, respectively………………………………………………3-26
Fig. 3-17. The IA incorporates with the new offset compensation circuitry…..3-30
Fig. 3-18. Nonoverlapping clock generator and clocking schemes for the offset- compensated IA……………………………………………..……….3-31
Fig. 3-19. Simulated step response of the proposed IA with the offset compensation at a supply voltage of 3.3 V…………………………………………..3-35
Fig. 3-20. Simulation made of the IA with an input sinusoidal signal at supply voltages of (a) 3.3 V, and (b) 5 V, respectively…………………..…..3-37
Fig. 3-21. Frequency response simulation of the IA in the TT case at supply voltages of (a) 3.3 V, and (b) 5 V, respectively……………………..………….3-39
Fig. 3-22. Simulation of the common-mode gain of the designed IA with offset cancellation at supply voltages of (a) 3.3 V, and (b) 5 V, respectively..3-40
Fig. 3-23. Schematic diagram of the designed GA……………………..……….3-42
Fig. 3-24. Simulation made of the GA with an input sinusoidal signal at supply voltages of (a) 3.3 V, and (b) 5 V, respectively…………..…………...3-44
Fig. 3-25. Frequency response simulation of the GA in the TT case at supply voltages of (a) 3.3 V, and (b) 5 V, respectively………………..……..3-45
Fig. 3-26. A continuous-time unity-gain second-order low pass filter………….3-47
Fig. 3-27. The equivalent resistance of a SC circuit…………………..…………3-48
Fig. 3-28. The fourth-order SCLPF realized in this study……………………….3-49
Fig. 3-29. Simulation made of the SCLPF with an input sinusoidal signal at supply voltages of (a) 3.3 V, and (b) 5 V, respectively……………………….3-51
Fig. 3-30. Simulated frequency response of the designed fourth-order SCLPF at a supply voltage of 3.3 V……………………………………………...3-52
Fig. 3-31. Schematic diagram of the integrated analog processor……..……..….3-55
Fig 3-32. Simulation results of the integrated analog processor circuit at the supply voltages of (a) 3.3 V, and (b) 5 V, respectively……………………….3-56
Fig. 3-33. A photomicrograph of the fabricated test chip………………..……...3-57
Fig. 4-1. Testing configuration of the fabricated test chip……………...………..4-2
Fig. 4-2. Measured output noise spectrum of the IA at a supply voltage of 3.3 V (a) without offset compensation, and (b) with offset compensation………4-4
Fig. 4-3. Measured output noise spectrum of the IA at a supply voltage of 5 V (a) without offset compensation, and (b) with offset compensation………4-5
Fig. 4-4. Measured output noise spectrum of the GA at supply voltages of (a) 3.3 V, and (b) 5 V, respectively………………………………….…………….4-7
Fig. 4-5. Measured output noise spectrum of the analog processor IC with offset compensation at supply voltages of (a) 3.3 V, and (b) 5 V, respectively.4-9
Fig. 4-6. Measured mean offset voltages of the IA at a supply voltage of 3.3 V (a) without offset compensation, and (b) with offset compensation……..4-11
Fig. 4-7. Measured mean offset voltages of the IA at a supply voltage of 5 V (a) without offset compensation, and (b) with offset compensation……..4-13
Fig. 4-8. Measured output signal of the IA with a square signal input of 40 mVP-P…………………………………………………………..…….4-14
Fig. 4-9. Measured offset voltage with an input common-mode voltage of 1.65 V DC at a supply voltage of 3.3 V………………………………..…….4-15
Fig. 4-10. Measured mean offset voltages of the GA at supply voltages of (a) 3.3 V, and (b) 5 V, respectively………………………………………………4-17
Fig. 4-11. Measured mean offset voltages of the SCLPF at supply voltages of (a) 3.3 V, and (b) 5 V, respectively………………………...…………………4-18
Fig. 4-12. Measured total static current consumption of the analog processor chip at supply voltages of (a) 3.3 V, and (b) 5 V, respectively…………...…..4-20
Fig. 4-13. Measured total dynamic current consumption of the analog processor chip at supply voltages of (a) 3.3 V, and (b) 5 V, respectively………….….4-21
Fig. 4-14. Measurement of the common-mode gain of the IA with an input sinusoidal signal at supply voltages of (a) 3.3 V, and (b) 5 V, respectively……………………………..……………………………4-23
Fig. 4-15. Measurement made of the IA with an input sinusoidal signal at a supply voltage of 3.3 V (a) without offset compensation, and (b) with offset compensation…………………………………………………………4-25
Fig. 4-16. Measurement of the IA with an input simulated ECG signal at a supply voltage of 3.3 V (a) with offset compensation, and (b) without offset compensation…………………………………………………………4-26
Fig. 4-17. Measurement made of the GA at a supply voltage of 3.3 V (a) with an input sinusoidal signal, and (b) with an input simulated ECG signal..4-28
Fig. 4-18. Measured frequency response of the SCLPF at a supply voltage of 3.3 V……………………………………………………………………4-29
Fig. 4-19. Measurement made of the analog processor IC at a supply voltage of 3.3 V (a) with an input sinusoidal signal, and (b) with an input simulated ECG signal……………………………………………………………4-30
Fig. 4-20. Measurement made of the analog processor IC at a supply voltage of 5 V (a) with an input sinusoidal signal, and (b) with an input simulated ECG signal………………………………………………………………….4-32
Fig. 5-1. Circuit implementations of (a) a GA, and (b) a fourth-order SCLPF that incorporate the offset compensation circuitry……………………..…...5-4

List of Tables
Table 1-1. Medical and physiological parameters.………………………..………1-4
Table 1-2. Comparison of the performance of several IAs in prior researches….1-6
Table 2-1. List of the pin description of the analog processor IC…………..…...2-9
Table 2-2. Specifications of the analog processor IC…………………………….2-10
Table 3-1. Critical parameters in the UMC 0.5-μm mixed-signal SPICE model.3-20
Table 3-2. Worst-case simulation of the designed OP……………………..……3-27
Table 3-3. Worst-case simulation of the designed IA…………………..……….3-41
Table 3-4. Worst-case simulation of the designed GA…………………………...3-46
Table 3-5. Worst-case simulation of the designed SCLPF……………………….3-53
Table 4-1. Measurements of the IA with offset compensation at supply voltages of 3.3 V and 5 V. (COS1 = COS2 = COS3 = 2 pF, R1 = R3 = 1 kΩ, R2 = R4 = 2 kΩ)………………………………………….…………………...4-34
Table 4-2. Comparison of the performance of several commercial IAs……..…..4-35
Table 4-3. Lists of the measurement results of the GA……………….………….4-35
Table 4-4. Measured characteristics of the SCLPF………………………………4-36
Table 4-5. Measured performance of the analog processor IC…………………..4-37
Table 4-6. Verification of the analog processor IC at a supply voltage of 3.3 V..4-38
Table 4-7. Verification of the analog processor IC at a supply voltage of 5 V…..4-39

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